DSPIC33FJ128MC506-I/PT Microchip Technology Inc., DSPIC33FJ128MC506-I/PT Datasheet - Page 111

• Manufacturer Part Number: DSPIC33FJ128MC506-I/PT
• Description: DSP, 16-Bit, 128KB Flash, 8KB RAM, 53 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC506-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 6-12:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
R/W-0
R/W-0
IC5IE
T6IE
T6IE: Timer6 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Unimplemented: Read as ‘0’
OC8IE: Output Compare Channel 8 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC7IE: Output Compare Channel 7 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC6IE: Output Compare Channel 6 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC6IE: Input Capture Channel 6 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
C1IE: ECAN1 Event Interrupt Enable bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DMA4IE
R/W-0
R/W-0
IC4IE
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
IC3IE
U-0
—
DMA3IE
OC8IE
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OC7IE
R/W-0
R/W-0
C1IE
C1RXIE
OC6IE
R/W-0
R/W-0
x = Bit is unknown
SPI2IE
dsPIC33F
OC5IE
R/W-0
R/W-0
DS70165E-page 109
SPI2EIE
R/W-0
R/W-0
IC6IE
bit 8
bit 0