DSPIC33FJ128MC506-I/PT Microchip Technology Inc., DSPIC33FJ128MC506-I/PT Datasheet - Page 183

• Manufacturer Part Number: DSPIC33FJ128MC506-I/PT
• Description: DSP, 16-Bit, 128KB Flash, 8KB RAM, 53 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC506-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.7.2
The DTCON2 SFR contains control bits that allow the
dead times to be assigned to each of the complemen-
tary outputs. Table 15-1 summarizes the function of
each dead-time selection control bit.
TABLE 15-1:
15.7.3
The amount of dead time provided by each dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value. The amount of dead
time provided by each unit may be set independently.
Four input clock prescaler selections have been pro-
vided to allow a suitable range of dead times, based on
the device operating frequency. The clock prescaler
option may be selected independently for each of the
two dead-time values. The dead-time clock prescaler
values are selected using the DTAPS<1:0> and
DTBPS<1:0> control bits in the DTCON1 SFR. One of
four clock prescaler options (T
may be selected for each of the dead-time values.
After the prescaler values are selected, the dead time
for each unit is adjusted by loading two 6-bit unsigned
values into the DTCON1 SFR.
The dead-time unit prescalers are cleared on the
following events:
• On a load of the down timer due to a duty cycle
• On a write to the DTCON1 or DTCON2 registers.
• On any device Reset.
© 2007 Microchip Technology Inc.
DTS1A
DTS1I
DTS2A
DTS2I
DTS3A
DTS3I
DTS4A
DTS4I
comparison edge event.
Note:
Bit
Selects PWM1L/PWM1H active edge dead time.
Selects PWM1L/PWM1H inactive edge
dead time.
Selects PWM2L/PWM2H active edge dead time.
Selects PWM2L/PWM2H inactive edge
dead time.
Selects PWM3L/PWM3H active edge dead time.
Selects PWM3L/PWM3H inactive edge
dead time.
Selects PWM4L/PWM4H active edge dead time.
Selects PWM4L/PWM4H inactive edge
dead time.
DEAD-TIME ASSIGNMENT
DEAD-TIME RANGES
The user should not modify the DTCON1
or DTCON2 values while the PWM mod-
ule is operating (PTEN = 1). Unexpected
results may occur.
DEAD-TIME SELECTION BITS
Function
CY
, 2 T
CY
, 4 T
CY
or 8 T
Preliminary
CY
)
15.8
An Independent PWM Output mode is required for
driving certain types of loads. A particular PWM output
pair is in the Independent Output mode when the cor-
responding PMODx bit in the PWMCON1 register is
set. No dead-time control is implemented between
adjacent PWM I/O pins when the module is operating
in the Independent PWM Output mode and both I/O
pins are allowed to be active simultaneously.
In the Independent PWM Output mode, each duty cycle
generator is connected to both of the PWM I/O pins in
an output pair. By using the associated Duty Cycle reg-
ister and the appropriate bits in the OVDCON register,
the user may select the following signal output options
for each PWM I/O pin operating in this mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
15.9
The PWM module produces single pulse outputs when
the PTCON control bits PTMOD<1:0> = 10. Only edge-
aligned outputs may be produced in the Single Pulse
mode. In Single Pulse mode, the PWM I/O pin(s) are
driven to the active state when the PTEN bit is set.
When a match with a Duty Cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PTPER register occurs, the PTMR
register is cleared, all active PWM I/O pins are driven
to the inactive state, the PTEN bit is cleared and an
interrupt is generated.
15.10 PWM Output Override
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states,
independent of the duty cycle comparison units.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains eight
bits, POVDxH<4:1> and POVDxL<4:1>, that determine
which PWM I/O pins will be overridden. The lower half
of
POUTxH<4:1> and POUTxL<4:1>, that determine the
state of the PWM I/O pins when a particular output is
overridden via the POVD bits.
15.10.1
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the comple-
ment of the corresponding PWMxH pin in the pair.
Dead-time insertion is still performed when PWM
channels are overridden manually.
the
Independent PWM Output
Single Pulse PWM Operation
OVDCON
COMPLEMENTARY OUTPUT MODE
register
dsPIC33F
contains
DS70165E-page 181
eight
bits,