DSPIC33FJ128MC506-I/PT Microchip Technology Inc., DSPIC33FJ128MC506-I/PT Datasheet - Page 155

• Manufacturer Part Number: DSPIC33FJ128MC506-I/PT
• Description: DSP, 16-Bit, 128KB Flash, 8KB RAM, 53 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC506-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 8-2:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4-0
Note 1:
R/W-0
R/W-0
ROI
PLLPOST<1:0>
This bit is cleared when the ROI bit is set and an interrupt occurs.
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: Processor Clock Reduction Select bits
000 = F
001 = F
010 = F
011 = F
100 = F
101 = F
110 = F
111 = F
DOZEN: DOZE Mode Enable bit
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
000 = FRC divide by 1
001 = FRC divide by 2
010 = FRC divide by 4
011 = FRC divide by 8 (default)
100 = FRC divide by 16
101 = FRC divide by 32
110 = FRC divide by 64
111 = FRC divide by 256
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
00 = Output/2
01 = Output/4
10 = Reserved (defaults to output/4)
11 = Output/8
Unimplemented: Read as ‘0’
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000 = Input/2
00001 = Input/3
11111 = Input/33
• • •
R/W-0
R/W-1
CLKDIV: CLOCK DIVISOR REGISTER
CY
CY
CY
CY
CY
CY
CY
CY
/1 (default)
/2
/4
/8
/16
/32
/64
/128
y = Value set from Configuration bits on POR
W = Writable bit
‘1’ = Bit is set
DOZE<2:0>
R/W-0
U-0
—
R/W-0
R/W-0
(1)
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DOZEN
R/W-0
R/W-0
(3)
(1)
PLLPRE<4:0>
R/W-1
R/W-0
FRCDIV<2:0>
x = Bit is unknown
dsPIC33F
R/W-0
R/W-0
DS70165E-page 153
R/W-0
R/W-0
(2)
bit 8
bit 0