DSPIC33FJ128MC506-I/PT Microchip Technology Inc., DSPIC33FJ128MC506-I/PT Datasheet - Page 228

• Manufacturer Part Number: DSPIC33FJ128MC506-I/PT
• Description: DSP, 16-Bit, 128KB Flash, 8KB RAM, 53 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC506-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC33F
REGISTER 19-1:
DS70165E-page 226
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
Note 1:
R/W-0 HC
UARTEN
WAKE
R/W-0
2:
This feature is only available for the 16x BRG mode (BRGH = 0).
Bit availability depends on pin availability.
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode.
0 = Continue module operation in Idle mode
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
11 =UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10 =UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 =UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00 =UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
0 = Baud rate measurement disabled or completed
URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
LPBACK
R/W-0
minimal
port latches
in hardware on following rising edge
cleared in hardware upon completion
U-0
—
UxMODE: UART
W = Writable bit
HC = Hardware cleared
‘1’ = Bit is set
R/W-0 HC
ABAUD
USIDL
R/W-0
x
MODE REGISTER
URXINV
IREN
R/W-0
R/W-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
RTSMD
BRGH
R/W-0
R/W-0
R/W-0
U-0
—
PDSEL<1:0>
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
(2)
UEN<1:0>
R/W-0
STSEL
R/W-0
(2)
bit 8
bit 0