DSPIC33FJ128MC506-I/PT Microchip Technology Inc., DSPIC33FJ128MC506-I/PT Datasheet - Page 174

• Manufacturer Part Number: DSPIC33FJ128MC506-I/PT
• Description: DSP, 16-Bit, 128KB Flash, 8KB RAM, 53 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC506-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC33F
14.3
The following steps should be taken when configuring
the output compare module for PWM operation:
1.
2.
3.
4.
5.
6.
14.3.1
The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using Equation 14-1:
EQUATION 14-2:
EXAMPLE 14-1:
DS70165E-page 172
1.
2.
Note:
Set the PWM period by writing to the selected
Timer Period register (PRy).
Set the PWM duty cycle by writing to the OCxRS
register.
Write the OxCR register with the initial duty cycle.
Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin utilization.
Configure the output compare module for one of
two PWM operation modes by writing to the Out-
put
(OCxCON<2:0>).
Set the TMRy prescale value and enable the
time base by setting TON = 1 (TxCON<15>).
Find the Timer Period register value for a desired PWM frequency that is 52.08 kHz, where F
prescaler setting of 1:1.
Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
Pulse-Width Modulation Mode
T
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s
PWM Period = (PR2 + 1) • T
19.2 s
PR2
PWM Resolution
CY
Compare
The OCxR register should be initialized
before the output compare module is first
enabled. The OCxR register becomes a
read-only duty cycle register when the
module is operated in the PWM modes.
The value held in OCxR will become the
PWM duty cycle for the first PWM period.
The contents of the Output Compare
Secondary register, OCxRS, will not be
transferred into OCxR until a time base
period match occurs.
PWM PERIOD
CALCULATION FOR MAXIMUM PWM RESOLUTION
PWM PERIOD AND DUTY CYCLE CALCULATIONS
= 62.5 ns
= (PR2 + 1) • 62.5 ns • 1
= 306
Mode
= log
= (log
= 8.3 bits
Maximum PWM Resolution (bits) =
bits,
10
10
(F
(16 MHz/52.08 kHz)/log
CY
CY
/F
• (Timer2 Prescale Value)
OCM<2:0>
PWM
)/log
Preliminary
10
2) bits
10
2) bits
EQUATION 14-1:
14.3.2
The PWM duty cycle is specified by writing to the OCxRS
register. The OCxRS register can be written to at any time,
but the duty cycle value is not latched into OCxR until a
match between PRy and TMRy occurs (i.e., the period is
complete). This provides a double buffer for the PWM duty
cycle and is essential for glitchless PWM operation. In the
PWM mode, OCxR is a read-only register.
Some important boundary parameters of the PWM duty
cycle include:
• If the Output Compare register, OCxR, is loaded
• If OCxR is greater than PRy (Timer Period register),
• If OCxR is equal to PRy, the OCx pin will be low
See Example 14-1 for PWM mode timing details.
Table 14-1 shows example PWM frequencies and
resolutions for a device operating at 10 MIPS.
PWM Period = [(PRy) + 1] • T
where:
PWM Frequency = 1/[PWM Period]
with 0000h, the OCx pin will remain low (0% duty
cycle).
the pin will remain high (100% duty cycle).
for one time base count value and high for all
other count values.
Note:
log
10
log
(
10
F
F
(2)
PWM
PWM DUTY CYCLE
A PRy value of N will produce a PWM
period of N + 1 time base count cycles. For
example, a value of 7 written into the PRy
register will yield a period consisting of
eight time base cycles.
CY
)
bits
CALCULATING THE PWM
PERIOD
© 2007 Microchip Technology Inc.
CY
CY
= 16 MHz and a Timer2
• (Timer Prescale Value)