DSPIC33FJ128MC506-I/PT Microchip Technology Inc., DSPIC33FJ128MC506-I/PT Datasheet - Page 180

• Manufacturer Part Number: DSPIC33FJ128MC506-I/PT
• Description: DSP, 16-Bit, 128KB Flash, 8KB RAM, 53 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC506-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

functions to the user. First, the control loop bandwidth is
buffered register. The PTPER buffer contents are loaded
dsPIC33F
15.1.4
In the Double Update mode (PTMOD<1:0> = 11), an
interrupt event is generated each time the PTMR regis-
ter is equal to zero, as well as each time a period match
occurs. The postscaler selection bits have no effect in
this mode of the timer.
The Double Update mode provides two additional
doubled because the PWM duty cycles can be updated,
twice per period. Second, asymmetrical center-aligned
PWM waveforms can be generated, which are useful for
minimizing output waveform distortion in certain motor
control applications.
15.1.5
The input clock to PTMR (F
options of 1:1, 1:4, 1:16 or 1:64, selected by control
bits, PTCKPS<1:0>, in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
The PTMR register is not cleared when PTCON is
written.
15.1.6
The match output of PTMR can optionally be post-
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling).
The postscaler counter is cleared when any of the
following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
The PTMR register is not cleared when PTCON is written.
15.2
PTPER is a 15-bit register and is used to set the counting
period for the PWM time base. PTPER is a double-
into the PTPER register at the following instants:
• Free-Running and Single-Shot modes: When the
• Up/Down Count modes: When the PTMR register
The value held in the PTPER buffer is automatically
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
DS70165E-page 178
Note:
PTMR register is reset to zero after a match with
the PTPER register.
is zero.
PWM Period
DOUBLE UPDATE MODE
Programming a value of 0x0001 in the
PWM Period register could generate a
continuous interrupt pulse and hence,
must be avoided.
PWM TIME BASE PRESCALER
PWM TIME BASE POSTSCALER
OSC
/4) has prescaler
Preliminary
The
Equation 15-1:
EQUATION 15-1:
If the PWM time base is configured for one of the Up/
Down Count modes, the PWM period will be twice the
value provided by Equation 15-1.
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
Equation 15-2:
EQUATION 15-2:
15.3
Edge-aligned PWM signals are produced by the module
when the PWM time base is in Free-Running or Single-
Shot mode. For edge-aligned PWM outputs, the output
has a period specified by the value in PTPER and a duty
cycle specified by the appropriate Duty Cycle register
(see Figure 15-2). The PWM output is driven active at
the beginning of the period (PTMR = 0) and is driven
inactive when the value in the Duty Cycle register
matches PTMR.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 15-2:
PTPER
PWM
0
Edge-Aligned PWM
PTMR
Value
Resolution =
Duty Cycle
T
PWM
period
Period
=
(PTMR Prescale Value)
PWM PERIOD
PWM RESOLUTION
EDGE-ALIGNED PWM
T
can
© 2007 Microchip Technology Inc.
CY
log (2 • T
• (PTPER + 1)
New Duty Cycle Latched
be
log (2)
PWM
determined
/T
CY
)
using