PIC32MX775F256H-80V/PT Microchip Technology, PIC32MX775F256H-80V/PT Datasheet - Page 163

• Manufacturer Part Number: PIC32MX775F256H-80V/PT
• Description: 256 KB Flash, 64 KB RAM, USB-OTG, Dual CAN, Ethernet, 80 MHz, 10-Bit ADC, DMA 64
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX775F256H-80V/PT

• Processor Series: PIC32MX7xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

27.0
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX family of devices. These
devices offer a total of nine methods and modes,
organized into two categories, that allow the user to
balance power consumption with device performance.
In all of the methods and modes described in this
section, power-saving is controlled by software.
27.1
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the PBCLK and by individually disabling
modules. These methods are grouped into the
following categories:
• FRC Run mode: the CPU is clocked from the FRC
• LPRC Run mode: the CPU is clocked from the
• S
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
27.2
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• P
• FRC Idle mode: the system clock is derived from
• S
© 2009-2011 Microchip Technology Inc.
clock source with or without postscalers.
LPRC clock source.
S
the P
operate. Peripherals continue to operate, but can
optionally be individually disabled.
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
the S
can optionally be individually disabled.
Note 1: This data sheet summarizes the features
OSC
OSC
OSC
OSC
OSC
OSC
Run mode: the CPU is clocked from the
clock source.
Idle mode: the system clock is derived from
Idle mode: the system clock is derived from
2: Some registers and associated bits
POWER-SAVING FEATURES
Power-Saving with CPU Running
CPU Halted Methods
. The system clock source continues to
. Peripherals continue to operate, but
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 10. “Power-
Saving Features” (DS61130) in the
“PIC32 Family Reference Manual” , which
is available from the Microchip web site
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
in
• LPRC Idle mode: the system clock is derived from
• Sleep mode: the CPU, the system clock source
27.3
Peripherals and the CPU can be halted or disabled to
further reduce power consumption.
27.3.1
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual
peripheral module sections for descriptions of
behavior in Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted
• The system clock source is typically shutdown.
• There can be a wake-up delay based on the
• The Fail-Safe Clock Monitor (FSCM) does not
• The BOR circuit, if enabled, remains operative
• The WDT, if enabled, is not automatically cleared
• Some peripherals can continue to operate at
• I/O pins continue to sink or source current in the
• Modules can be individually disabled by software
PIC32MX5XX/6XX/7XX
the LPRC. Peripherals continue to operate, but
can optionally be individually disabled. This is the
lowest power mode for the device with a clock
running.
and any peripherals that operate from the system
clock source are Halted. Some peripherals can
operate in Sleep using specific clock sources.
This is the lowest power mode for the device.
See
Method”
oscillator selection
operate during Sleep mode
during Sleep mode
prior to entering Sleep mode
limited functionality in Sleep mode. These
peripherals include I/O pins that detect a change
in the input signal, WDT, ADC, UART and
peripherals that use an external clock input or the
internal LPRC oscillator (e.g., RTCC, Timer1 and
Input Capture).
same manner as they do when the device is not in
Sleep
prior to entering Sleep in order to further reduce
consumption
Section 27.3.3 “Peripheral Bus Scaling
Power-Saving Operation
SLEEP MODE
for specific information.
DS61156G-page 163