PIC32MX775F256H-80V/PT Microchip Technology, PIC32MX775F256H-80V/PT Datasheet - Page 78

• Manufacturer Part Number: PIC32MX775F256H-80V/PT
• Description: 256 KB Flash, 64 KB RAM, USB-OTG, Dual CAN, Ethernet, 80 MHz, 10-Bit ADC, DMA 64
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX775F256H-80V/PT

• Processor Series: PIC32MX7xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

TABLE 4-11:
Legend:
Note
5000
5010
5020
5030
5040
5050
5060
5100
5120
5130
5140
5150
5160
5200
5210
5110
1:
I2C3STAT
I2C4STAT
I2C5STAT
I2C3CON
I2C3MSK
I2C3BRG
I2C4CON
I2C4MSK
I2C4BRG
I2C5CON
I2C3TRN
I2C3RCV
I2C4ADD
I2C4TRN
I2C4RCV
I2C5DD
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
for more information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP
ACKSTAT
ACKSTAT
ACKSTAT
31/15
ON
ON
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRSTAT
TRSTAT
TRSTAT
30/14
FRZ
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCLREL
SCLREL
SCLREL
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STRICT
STRICT
STRICT
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
A10M
A10M
A10M
BCL
BCL
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
GCSTAT
GCSTAT
GCSTAT
DISSLW
DISSLW
DISSLW
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD10
ADD10
ADD10
SMEN
SMEN
SMEN
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
IWCOL
IWCOL
IWCOL
GCEN
GCEN
GCEN
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Baud Rate Generator Register
Baud Rate Generator Register
STREN
STREN
STREN
I2COV
I2COV
I2COV
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ACKDT
ACKDT
ACKDT
21/5
D/A
D/A
D/A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
MSK<9:0>
ADD<9:0>
MSK<9:0>
ACKEN
ACKEN
ACKEN
Transmit Register
Transmit Register
20/4
Receive Register
Receive Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P
P
P
RCEN
RCEN
RCEN
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
S
S
Section 12.1.1 “CLR, SET and INV Registers”
18/2
PEN
R/W
PEN
R/W
PEN
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RSEN
RSEN
RSEN
17/1
RBF
RBF
RBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16/0
SEN
SEN
SEN
TBF
TBF
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000