PIC32MX775F256H-80V/PT Microchip Technology, PIC32MX775F256H-80V/PT Datasheet - Page 49

• Manufacturer Part Number: PIC32MX775F256H-80V/PT
• Description: 256 KB Flash, 64 KB RAM, USB-OTG, Dual CAN, Ethernet, 80 MHz, 10-Bit ADC, DMA 64
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX775F256H-80V/PT

• Processor Series: PIC32MX7xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

3.0
The MIPS32
PIC32MX5XX/6XX/7XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2)
FIGURE 3-1:
© 2009-2011 Microchip Technology Inc.
- Multiply-accumulate and multiply-subtract
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
Note 1: This data sheet summarizes the features
instructions
2: Some registers and associated bits
CPU
Features
CPU
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS61113)
Reference Manual”, which is available
from the Microchip web site
chip.com/PIC32). Resources for the
MIPS32
available at http://www.mips.com.
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
®
M4K
®
®
Processor core is the heart of the
MIPS
M4K
(RF/ALU/Shift)
Coprocessor
in
Execution
®
System
®
Core
MDU
the
M4K
Processor Core are
®
“PIC32
PROCESSOR CORE BLOCK DIAGRAM
(www.micro-
Family
FMT
in
• MIPS16e
• Simple Fixed Mapping Translation (FMT)
• Simple dual bus interface
• Autonomous multiply/divide unit
• Power control
• EJTAG debug and instruction trace
Bus Interface
Management
PIC32MX5XX/6XX/7XX
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
- Bit field manipulation instructions
- 16-bit encoding of 32-bit instructions to
- Special PC-relative instructions for efficient
- SAVE and RESTORE macro instructions for
- Improved support for handling 8 and 16-bit
mechanism
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
- Maximum issue rate of one 32x16 multiply
- Maximum issue rate of one 32x32 multiply
- Early-in iterative divide. Minimum 11 and
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
- Extensive use of local gated clocks
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
- PC tracing with trace compression
for interrupt handlers
improve code density
loading of addresses and constants
setting up and tearing down stack frames
within subroutines
data types
interrupt latency
per clock
every other clock
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
instruction)
Power
EJTAG
Trace
TAP
®
code compression
Dual Bus I/F
Debug I/F
Off-Chip
Trace I/F
DS61156G-page 49