ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet
ELLXT971ABE.A4
Specifications of ELLXT971ABE.A4
Available stocks
Related parts for ELLXT971ABE.A4
ELLXT971ABE.A4 Summary of contents
Page 1
... The LXT971A Transceiver is IEEE compliant, and provides a Low Voltage Positive Emitter Coupled Logic (LVPECL) interface for use with 100BASE-FX fiber networks. (This ® document also supports the Intel LXT971 Transceiver.) The LXT971A Transceiver supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT971A Transceiver can be set using auto-negotiation, parallel detection, or manual control ...
Page 2
... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
Page 3
... Contents 1.0 Introduction to This Document ......................................................................................... 11 1.1 Document Overview ............................................................................................11 1.2 Related Documents............................................................................................. 11 2.0 Block Diagram for Intel 3.0 Ball and Pin Assignments for Intel 4.0 Signal Descriptions for Intel 5.0 Functional Description...................................................................................................... 24 5.1 Device Overview .................................................................................................25 5.1.1 Comprehensive Functionality ................................................................. 25 5.1.2 Optimal Signal Processing Architecture ................................................. 25 5 ...
Page 4
... Electrical Parameters .......................................................................................... 70 7.2 Timing Diagrams ................................................................................................. 76 8.0 Register Definitions - IEEE Base Registers ..................................................................... 88 9.0 Register Definitions - Product-Specific Registers ............................................................ 96 ® 10.0 Intel LXT971A Transceiver Package Specifications .................................................... 105 10.1 Top Label Markings........................................................................................... 107 11.0 Product Ordering Information ......................................................................................... 109 4 Datasheet Document Number: 249414-003 Revision Date: 25-Oct-2005 ...
Page 5
... PHY Identifier Bit Mapping ................................................................................. 91 ® 43 Intel LXT971A Transceiver PBGA Package Specification .............................. 105 ® 44 Intel LXT971A Transceiver LQFP Package Specifications ............................. 106 45 Sample LQFP Package - Intel 46 Sample Pb-Free (RoHS-Compliant) LQFP Package - ® Intel LXT971A Transceiver.............................................................................. 107 47 Sample TPBGA Package - Intel Datasheet Document Number: 249414-003 Revision Date: 25-Oct-2005 ® ...
Page 6
... Magnetics Requirements .................................................................................... 62 19 I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................ 62 20 Absolute Maximum Ratings for Intel 21 Recommended Operating Conditions for Intel 22 Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) .............. 72 23 Digital I/O Characteristics 24 I/O Characteristics - REFCLK/XI and XO Pins.................................................... 73 25 I/O Characteristics - LED/CFG Pins ...
Page 7
... LED Configuration Register - Address 20, Hex 14 ............................................ 101 60 Digital Configuration Register - Address 26, Hex 1A ........................................ 102 61 Digital Configuration Register - Address 26, Hex 1A ........................................ 103 62 Transmit Control Register - Address 30, Hex 1E .............................................. 104 63 Product Ordering Information ............................................................................109 Datasheet Document Number: 249414-003 Revision Date: 25-Oct-2005 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 7 ...
Page 8
... LXT971A Transceiver Revision 002 (Sheet Revision Date: August 6, 2002 Description (replaced TEST1 and TEST0 with GND). Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and multi- Table 3 “LXT971A Network Interface Signal Descriptions”. Descriptions”. Modes”. Section 3.2.1.2, “Fiber Strength” ...
Page 9
... Conditions”: Added Typ values to Vcc current. Pins”. Pins”. Pin”. Characteristics”. Map”. (Added Table 26 information). Information”. ® Intel LXT971A Transceiver Revision 001 Revision Date: January 2001 Description Circuitry”. Circuitry”. Translator”. 26)”. 30)”. ...
Page 10
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 10 Datasheet Document Number: 249414-003 Revision Date: 25-Oct-2005 ...
Page 11
... This document includes the following subjects: • Chapter 2.0, “Block Diagram for Intel® LXT971A Transceiver” • Chapter 3.0, “Ball and Pin Assignments for Intel® LXT971A Transceiver” • Chapter 4.0, “Signal Descriptions for Intel® LXT971A Transceiver” • ...
Page 12
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 2.0 Block Diagram for Intel Figure block diagram of the LXT971A Transceiver. ® Figure 1. Intel LXT971A Transceiver Block Diagram RESET_L Management / ADDR[4:0] Mode Select MDIO Register Set Logic MDC MDINT_L MDDIS TX_EN TXD[3:0] Parallel/Serial ...
Page 13
... Ball and Pin Assignments for Intel Transceiver Figure 2 shows the ball assignments for the LXT971A Transceiver 64-ball PBGA package. Figure 2. Ball Assignments for Intel 1 MDINT A _L REF B CLK/XI RESET SLEW0 SLEW1 E ADDR0 ADDR1 F ADDR3 ADDR2 G ADDR4 H RBIAS TPFOP 1 Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® ...
Page 14
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Figure 3 shows the pin assignments for the LXT971A Transceiver LQFP package. ® Figure 3. Pins for Intel LXT971A Transceiver 64-Pin LQFP Package 1 REFCLK/ MDDIS 4 RESET_L 5 TXSLEW0 6 TXSLEW1 7 GND 8 VCCIO GND 12 ADDR0 13 ADDR1 14 ADDR2 15 ADDR3 ...
Page 15
... TPFIP 24 TPFIN 25 GND 26 SD/TP_L 27 TDI 28 TDO 29 TMS 30 TCK 31 TRST_L 32 SLEEP 33 PAUSE 34 GND 35 GND 36 LED/CFG3 Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Symbol Type – – – – – – – – – ...
Page 16
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver ® Table 2. Intel LXT971A Transceiver LQFP Numeric Pin List (Sheet Pin 37 LED/CFG2 38 LED/CFG1 39 PWRDWN 40 VCCIO 41 GND 42 MDIO 43 MDC RXD3 46 RXD2 47 RXD1 48 RXD0 49 RX_DV 50 GND 51 VCCD 52 RX_CLK 53 RX_ER 54 TX_ER 55 TX_CLK 56 TX_EN 57 TXD0 58 TXD1 59 TXD2 ...
Page 17
... Table 6, “Intel® LXT971A Transceiver Network Interface Signal Descriptions” • Table 7, “Intel® LXT971A Transceiver Standard Bus and Interface Signal Descriptions” • Table 8, “Intel® LXT971A Transceiver Configuration and LED Driver Signal Descriptions” • Table 9, “Intel® LXT971A Transceiver Power, Ground, No-Connect Signal Descriptions” • ...
Page 18
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 4 lists signal descriptions of the LXT971A Transceiver MII data interface pins. ® Table 4. Intel LXT971A Transceiver MII Data Interface Signal Descriptions (Sheet PBGA LQFP Symbol Pin# Pin TXD3 B3 59 TXD2 C4 58 TXD1 A4 57 ...
Page 19
... A1 64 MDINT_L Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Type Signal Description Carrier Sense. During half-duplex operation (Register bit 0.8 = 0), the LXT971A Transceiver asserts this output when either transmitting or receiving data packets. ...
Page 20
... Pin TPFOP H3 20 TPFON H4 23 TPFIP H5 24 TPFIN G2 26 SD/TP_L Table 7 lists signal descriptions of the LXT971A Transceiver standard bus and interface signals. ® Table 7. Intel LXT971A Transceiver Standard Bus and Interface Signal Descriptions PBGA LQFP Symbol Pin# Pin ADDR0 Symbol Type Twisted-Pair/Fiber Outputs, Positive and Negative ...
Page 21
... Configuration Register - Address 20, Hex 14” on page LED/CFG2 I/O Configuration Inputs 1-3. LED/CFG3 These pins also provide initial configuration settings. (For details, see Table 12, “Hardware Configuration Settings for Intel® LXT971A Transceiver” on page Signal Description Slew Rate (Rise and Fall Time ...
Page 22
... C3, G7, 41 G3, G4 21 Table 10 lists signal descriptions of LXT971A Transceiver Joint Test Action Group (JTAG) pins. Note JTAG port is not used, these pins do not need to be terminated. ® Table 10. Intel LXT971A Transceiver JTAG Test Signal Descriptions PBGA LQFP Pin# Pin ...
Page 23
... LXT971A Transceiver. Note: • Driven High (Logic 1) • Driven Low (Logic 0) • High Impedance • Internal Pull-Down (Weak) ® Table 11. Intel LXT971A Transceiver Pin Types and Modes Modes RXD3:0 HWReset DL SFTPWRDN DL HWPWRDN High Z HZ with ...
Page 24
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 5.0 Functional Description This chapter has the following sections: • Section 5.1, “Device Overview” • Section 5.2, “Network Media / Protocol Support” • Section 5.3, “Operating Requirements” • Section 5.4, “Initialization” ...
Page 25
... DSP engines. This logic switching noise can be a considerable source of EMI generated on the device’s power supplies. The OSP-based LXT971A Transceiver provides improved data recovery, EMI performance, and low power consumption. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 25 ...
Page 26
... The network interface port consists of five external pins (two differential signal pairs and a signal detect pin). The I/O pins are shared between twisted-pair (TP) and fiber. For specific pin assignments, see Chapter 4.0, “Signal Descriptions for Intel® LXT971A The LXT971A Transceiver output drivers can generate one of the following outputs: • ...
Page 27
... Only a transformer, RJ-45 connector,load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT971A Transceiver has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the designer to match the output waveform to the magnetic characteristics ...
Page 28
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 100BASE-FX Far-End Fault Indication. The LXT971A Transceiver independently detects signal faults from the local fiber transceivers through the SD/TP_L pin. The LXT971A Transceiver also uses Register bit 1.4 to report Remote Fault indications received from its link partner. The LXT971A Transceiver ORs both fault conditions to set bit 1.4 to ‘ ...
Page 29
... MDIO Management Interface MDIO management interface topics include the following: • Section 5.2.3.1.1, “MDIO Addressing for Intel® LXT971A Transceiver” • Section 5.2.3.1.2, “MDIO Frame Structure” • Section 5.2.3.1.3, “MII Interrupts” ...
Page 30
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 5.2.3.1.2 MDIO Frame Structure The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is shown in Figure 4 and MDIO Interface timing is given in Figure 4. Management Interface Read Frame Structure MDC MDIO 32 " ...
Page 31
... Auto-negotiation complete — Speed status change — Duplex status change — Link status change • Register 19 provides the interrupt status. ® Figure 6. Intel LXT971A Transceiver MII Interrupt Logic Even X Mask Reg Even X Status Reg Force Interrupt 5.2.3.2 Hardware Control Interface The LXT971A Transceiver provides a Hardware Control Interface for applications where the MDIO is not desired ...
Page 32
... XI. The connection of a clock source to the XI pin requires the XO pin to be left open. To minimize transmit jitter, Intel recommends a crystal-based clock instead of a derived clock (that is, a PLL- based clock). A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. For clock timing requirements, see Characteristics - REFCLK/XI and XO Pins” ...
Page 33
... Section 5.4.1, “MDIO Control Mode and Hardware Control Mode” • Section 5.4.2, “Reduced-Power Modes” • Section 5.4.3, “Reset for Intel® LXT971A Transceiver” • Section 5.4.4, “Hardware Configuration Settings” When the LXT971A Transceiver is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link ...
Page 34
... LXT971A Single-Port 10/100 Mbps PHY Transceiver Figure 7 shows the initialization sequence for the LXT971A Transceiver. The configuration bits may be set by the Hardware Control or MDIO interface. Figure 7. Initialization Sequence for Intel MDIO Control MDIO Controlled Operation (MDIO Writes Enabled) Reset MDIO Registers to ...
Page 35
... Software power-down control is provided by Register bit 0.11 in the Control Register. (See Table 45 on page 88.) • The network port is shut down. • The MDIO registers remain accessible. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver During soft power-down, the following conditions are true: 35 ...
Page 36
... Note: Sleep mode is not functional in fiber network applications. 5.4.3 Reset for Intel The LXT971A Transceiver provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. For a software reset, Register bit 0. For register bit definitions used for software reset, see Table 45, “ ...
Page 37
... Pin 1 Settings Control Register BASE-TX Auto- Speed Full Neg. Duplex 0.12 0.13 0 Chapter 3.0, “Ball and Pin Assignments for Intel® Auto-Negotiation Advertisement Register 100 100 10 10 BASE BASE-T BASE-T Full- -TX Full- Duplex Duplex 4.8 4.7 4.6 4.5 N/A Auto-Negotiation Advertisement ...
Page 38
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver As shown in Figure 8, Figure 8. Hardware Configuration Settings 38 the LED drivers can operate as either open-drain or open-source circuits. Configuration Bit = 1 LED/CFG Pin LED/CFG Pin Configuration Bit = 0 B3472-01 1. The LED/CFG pins automatically adjust their polarity upon power-up or reset. ...
Page 39
... Figure 9 shows an overview of link establishment for the LXT971A Transceiver. Note: When a link is established by using parallel detection, the LXT971A Transceiver sets the duplex mode to half-duplex, as defined by the IEEE 802.3 standard. ® Figure 9. Intel LXT971A Transceiver Link Establishment Overview Disable Auto-Negotiation Go To Forced ...
Page 40
... Controlling Auto-Negotiation When auto-negotiation is controlled by software, Intel recommends the following steps: 1. After power-up, power-down, or reset, the power-down recovery time (specified in “Intel® LXT971A Transceiver RESET_L Pulse Width and Recovery Timing” on page must be exhausted before proceeding. 2. Set the Auto-Negotiation Advertisement Register bits. ...
Page 41
... TXD[3:0] The LXT971A Transceiver supplies both clock signals as well as separate outputs for carrier sense and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 41 ...
Page 42
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 5.6.1 MII Clocks The LXT971A Transceiver is the master clock source for data transmission, and it supplies both MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. • When the link is operating at 100 Mbps, the clocks are set to 25 MHz. ...
Page 43
... For 10BASE-T links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Link-Down Condition/Auto-Negotiate Enabled Any 2.5 MHz Clock ...
Page 44
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 5.6.4 Carrier Sense Carrier Sense (CRS asynchronous output. • CRS is always generated when the LXT971A Transceiver receives a packet from the line. • CRS is also generated when the LXT971A Transceiver is in half-duplex mode when a packet is transmitted ...
Page 45
... Figure 13 shows LXT971A Transceiver operational and test loopback paths. (An internal digital loopback path is not shown.) For more information on loopback functions, see Sense, Loopback, and Collision Conditions” on page ® Figure 13. Intel LXT971A Transceiver Loopback Paths Intel® LXT971A Transceiver MII 5.6.7.1 Operational Loopback • ...
Page 46
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 5.6.7.2 Internal Digital Loopback (Test Loopback) A test loopback function is provided for diagnostic testing of the LXT971A Transceiver. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT971A Transceiver and returned to the MAC. ...
Page 47
... LVPECL interface. An external 100BASE-FX transceiver module is required to complete the fiber connection. To enable 100BASE-FX operation, auto-negotiation must be disabled and fiber mode selected. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver in 100BASE-TX mode, the LXT971A Transceiver scrambles and transmits 4B/ ...
Page 48
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Figure 16 shows normal reception with no errors. Figure 16. 100BASE-TX Reception with No Errors RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA RX_ER As shown in Figure asserts RX_ER. Figure 17. 100BASE-TX Reception with Invalid Symbol RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA ...
Page 49
... Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 19. 100BASE-TX Transmission with Collision TX_CLK TX_EN TXD<3:0> P CRS COL Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Figure 19. R ...
Page 50
... Section 5.7.3.2, “Physical Medium Attachment Sublayer” • Section 5.7.3.3, “Twisted-Pair Physical Medium Dependent Sublayer” • Section 5.7.3.4, “Fiber PMD Sublayer” Figure 20 shows the LXT971A Transceiver protocol sublayers. ® Figure 20. Intel LXT971A Transceiver Protocol Sublayers PCS Sublayer PMA Sublayer PMD Sublayer ...
Page 51
... The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T /H/ (Error) code group is used to signal an error condition. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 5B Code Name ...
Page 52
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 14. 4B/5B Coding (Sheet Code Code Type CONTROL Undefined Undefined Undefined Undefined Undefined Undefined Undefined INVALID Undefined Undefined Undefined Undefined Undefined Undefined 1. The /I/ (Idle) code group is sent continuously between frames. 2. The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. ...
Page 53
... However, in this case RX_ER is asserted for one clock cycle when CRS is de- asserted. Intel does not recommend using CRS for Interframe Gap (IFG) timing for the following reasons: • CRS de-assertion time is slightly longer than CRS assertion time result, an IFG interval appears somewhat shorter to the MAC than it actually is on the wire. • ...
Page 54
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 5.7.3.3 Twisted-Pair Physical Medium Dependent Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides signal scrambling and de- scrambling functions, line coding and decoding functions (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), as well as receiving, polarity correction, and baseline wander correction functions. ...
Page 55
... MII, padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 55, “Configuration Register - 97. 55 ...
Page 56
... If link pulses or data are not received by the maximum receive time-out period (96 to 128 ms), the polarity state is reset to a non-inverted state. 56 Figure 34, “Intel® LXT971A Transceiver 82. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ...
Page 57
... Transceiver uses Register bit 6.5 to indicate when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Register bits 6.1 and 6.5 are cleared when read. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 57 ...
Page 58
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 5.9.3 LED Functions The LXT971A Transceiver has these direct LED driver pins: LED1/CFG1, LED2/CFG2, and LED3/CFG3. On power-up, all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register Configuration Register - Address 20, Hex 14” ...
Page 59
... Figure 21. LED Pulse Stretching Event LED stretch Note: The direct drive LED outputs in this diagram are shown as active L ow. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver stretch stretch B3475-01 59 ...
Page 60
... The LXT971A Transceiver includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. Note: For the related BSDL file, contact your local sales office or access the Intel website (www.intel.com). 5.10.1 Boundary Scan Interface The boundary scan interface consists of five pins (TMS, TDI, TDO, TRST_L, and TCK) ...
Page 61
... Table 17. Device ID Register for Intel Bits 31:28 Bits 27:12 Version Part ID (Hex) XXXX 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC (1111 1110), which becomes 111 1110. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® ...
Page 62
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 6.0 Application Information 6.1 Magnetics Information The LXT971A Transceiver requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated protect the circuitry from static voltages across the connectors and cables. For transformer/magnetics requirements, see ...
Page 63
... Figure 22 shows the LXT971A Transceiver in a typical twisted-pair interface, with the RJ-45 connections crossed over for a Switch configuration. ® Figure 22. Intel LXT971A Transceiver Typical Twisted-Pair Interface - Switch Intel® LXT971A Transceiver 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2 ...
Page 64
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver ® Figure 23. Intel LXT971A Transceiver Typical Twisted-Pair Interface - NIC Intel® LXT971A Transceiver 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2.5 V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 Ω ...
Page 65
... Figure 24 show a typical media independent interface (MII) for the LXT971A Transceiver. ® Figure 24. Intel LXT971A Transceiver Typical Media Independent Interface MAC Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver TX_EN TX_ER TXD[3:0] TX_CLK RX_CLK Intel® ...
Page 66
... The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with the LXT971A Transceiver. For details on fiber interface designs and recommendations for Intel PHYs, see the document on 100BASE-FX fiber optics listed in ...
Page 67
... Figure 25 shows a typical example of an interface between the LXT971A Transceiver and a 3.3 V fiber transceiver. Figure 25. Typical Interface - Intel TPFON TPFOP Intel® LXT971A Transceiver SD/TP_L TPFIN TPFIP 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® ...
Page 68
... V LVPECL input levels. • The signal detect pin fiber transceiver interface should use the logic translator circuitry as shown in Figure 26 shows a typical example of an interface between the LXT971A Transceiver and fiber transceiver. Figure 26. Typical Interface - Intel TPFON TPFOP Intel® LXT971A Transceiver SD/TP_L ...
Page 69
... Figure 27 (a close-up view of Transceiver and a PECL-to-PECL logic translator. Figure 27. Typical Interface - Intel Translator 0.01 μ Ω PECL Input Signal (5V Fiber 130 Ω Txcvr) Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Figure 26) shows typical interface between the LXT971A ® ...
Page 70
... Supply Voltage Operating temperature LXT971A_C (Commercial) Operating temperature LXT971A_E (Extended) Storage Temperature Table 21 lists the recommended operating conditions for the LXT971A Transceiver. Table 21. Recommended Operating Conditions for Intel Parameter Recommended operating temperature - LXT971A_C (Commercial) Recommended operating temperature - LXT971A_E (Extended) Recommended supply voltage ...
Page 71
... Table 21. Recommended Operating Conditions for Intel Parameter Sleep Mode Hard Power Down Soft Power Down Auto-Negotiation 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. Voltages are with respect to ground unless otherwise specified. ...
Page 72
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 22 lists digital I/O characteristics for all pins except the MII, XI/XO, and LED/CFG pins. Table 22. Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) Parameter Input Low voltage Input High voltage ...
Page 73
... Mode Normal Operation – SD Input from Fiber Transceiver Input Low Voltage Input High Voltage 1. Typical values are for design aid only, not guaranteed, and not subject to production testing. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 1 Symbol Min Typ V – ...
Page 74
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 27 lists the 100BASE-TX characteristics. Table 27. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 Ω ...
Page 75
... Link Transmit Period Link Pulse Width 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. Table 31 lists the thermal characteristics. ® Table 31. Intel LXT971A Transceiver Thermal Characteristics Parameter Package Theta-JA Theta-JC Psi - JT ...
Page 76
... LXT971A Transceiver 100BASE-TX Receive Timing - 4B Mode 0 ns TPFI CRS RX_DV RXD[3:0] RX_CLK COL ® Table 32. Intel LXT971A Transceiver 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD[3:0], RX_DV, RX_ER RX_CLK High RXD[3:0], RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD[3:0], RX_DV Receive start of “J” to CRS asserted Receive start of “ ...
Page 77
... Figure 29. Intel LXT971A Transceiver 100BASE-TX Transmit Timing - 4B Mode TXCLK TX_EN TXD[3:0] TPFO CRS ® Table 33. Intel LXT971A Transceiver 100BASE-TX Transmit Timing Parameters Parameter TXD[3:0], TX_EN, TX_ER TX_CLK High TXD[3:0], TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted ...
Page 78
... LXT971A Transceiver 100BASE-FX Receive Timing TPFI CRS RX_DV RXD[3:0] RX_CLK COL ® Table 34. Intel LXT971A Transceiver 100BASE-FX Receive Timing Parameters Parameter RXD[3:0], RX_DV, set up to RX_CLK High RXD[3:0], RX_DV, RX_ER from RX_CLK High CRS asserted to RXD[3:0], RX_DV Receive start of “J” to CRS asserted Receive start of “ ...
Page 79
... Figure 31. Intel LXT971A Transceiver 100BASE-FX Transmit Timing TXCLK TX_EN TXD[3:0] TPFO CRS ® Table 35. Intel LXT971A Transceiver 100BASE-FX Transmit Timing Parameters Parameter TXD[3:0], TX_EN, TX_ER TX_CLK High TXD[3:0], TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted ...
Page 80
... LXT971A Transceiver 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPFI COL ® Table 36. Intel LXT971A Transceiver 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPFIP RXD out (Rx latency) CRS asserted to RXD, RX_DV, ...
Page 81
... Figure 33. Intel LXT971A Transceiver 10BASE-T Transmit Timing TX_CLK TXD, TX_EN, TX_ER CRS TPFO ® Table 37. Intel LXT971A Transceiver 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted ...
Page 82
... LXT971A Transceiver 10BASE-T Jabber and Unjabber Timing TX_EN TXD COL ® Table 38. Intel LXT971A Transceiver 10BASE-T Jabber and Unjabber Timing Parameter Maximum transmit time Unjabber time 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing ...
Page 83
... Figure 35. Intel LXT971A Transceiver 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN COL ® Table 39. Intel LXT971A Transceiver 10BASE-T SQE (Heartbeat) Timing Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing ...
Page 84
... LXT971A Transceiver Auto-Negotiation and Fast Link Pulse Timing TPFOP ® Figure 37. Intel LXT971A Transceiver Fast Link Pulse Timing TPFOP ® Table 40. Intel LXT971A Transceiver Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse ...
Page 85
... LXT971A Transceiver MDIO Input Timing MDC MDIO ® Figure 39. Intel LXT971A Transceiver MDIO Output Timing MDC MDIO ® Table 41. Intel LXT971A Transceiver MDIO Timing Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY MDC period 1. Typical values are at 25° ...
Page 86
... Figure 40. Intel LXT971A Transceiver Power-Up Timing VCC MDIO, and so on ® Table 42. Intel LXT971A Transceiver Power-Up Timing Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing. ...
Page 87
... Figure 41. Intel LXT971A Transceiver RESET_L Pulse Width and Recovery Timing RESET_L MDIO, and so on ® Table 43. Intel LXT971A Transceiver RESET_L Pulse Width and Recovery Timing Parameter RESET_L pulse width RESET_L recovery delay 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing ...
Page 88
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Base Registers This chapter includes definitions for the IEEE base registers used by the LXT971A Transceiver. Chapter 9.0, “Register Definitions - Product-Specific Registers” product-specific LXT971A Transceiver registers, which are defined in accordance with the IEEE 802 ...
Page 89
... Not Supported Read Only LL = Latching Low LH = Latching High Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Description 0 = Disable auto-negotiation process 1 = Enable auto-negotiation process 0 = Normal operation 1 = Power-down 0 = Normal operation 1 = Electrically isolate PHY from MII ...
Page 90
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 46. MII Status Register #1 - Address 1, Hex 1 (Sheet Bit Name 100BASE-T2 Half- Duplex 1.9 Not Supported 1.8 Extended Status 1.7 Reserved MF Preamble 1.6 Suppression Auto-Negotiation 1.5 complete 1.4 Remote Fault 1.3 Auto-Negotiation Ability 1.2 Link Status 1 ...
Page 91
... Figure 42. PHY Identifier Bit Mapping PHY ID Register #1 (Address 2) = 0013 Note: The Intel OUI is 00207B hex Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Description 6 bits containing manufacturer’s part number. 4 bits containing manufacturer’s revision number ...
Page 92
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 49 lists auto-negotiation advertisement bits. Table 49. Auto-Negotiation Advertisement Register - Address 4, Hex 4 Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved Asymmetric 4.11 Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX 4.8 Full-duplex 4 ...
Page 93
... RO = Read Only Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Description 0 = Link Partner has no ability to send multiple pages Link Partner has ability to send multiple pages Link Partner has not received Link Code Word from the LXT971A Transceiver ...
Page 94
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 51 lists auto-negotiation expansion bits. Table 51. Auto-Negotiation Expansion - Address 6, Hex 6 Bit Name 6.15:6 Reserved 6.5 Base Page Parallel 6.4 Detection Fault Link Partner 6.3 Next Page Able 6.2 Next Page Able 6.1 Page Received Link Partner A/N 6 ...
Page 95
... Code Field Read Only. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Description 0 = Last page 1 = Additional next pages follow Ignore when read Register bits 7.10:0 are user defined Register bits 7.10.0 follow IEEE message page format ...
Page 96
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver 9.0 Register Definitions - Product-Specific Registers This chapter includes definitions of product-specific LXT971A Transceiver registers that are defined in accordance with the IEEE 802.3 standard for adding unique device functions. (For definitions of the IEEE base registers used by the LXT971A Transceiver, see “ ...
Page 97
... Fiber Select 1. R/W = Read /Write Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read Normal operation 1 = Force Link pass 0 = Normal operation 1 = Disable Twisted Pair transmitter 0 = Normal operation 1 = Bypass Scrambler and Descrambler Write as ‘ ...
Page 98
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 56 lists register #2 status bits. Table 56. Status Register #2 - Address 17, Hex 11 Bit Name 17.15 Reserved 17.14 10/100 Mode 17.13 Transmit Status 17.12 Receive Status 17.11 Collision Status 17.10 Link 17.9 Duplex Mode 17.8 Auto-Negotiation Auto-Negotiation 17 ...
Page 99
... TINT 1. R/W = Read /Write Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Mask for Auto Negotiate Complete not allow event to cause interrupt. ...
Page 100
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 58 lists status change bits. Table 58. Status Change Register - Address 19, Hex 13 Bit Name 19.15:9 Reserved 19.8 Reserved 19.7 ANDONE 19.6 SPEEDCHG 19.5 DUPLEXCHG 19.4 LINKCHG 19.3 Reserved 19.2 MDINT_L 19.1 Reserved 19.0 Reserved 1 ...
Page 101
... Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) ...
Page 102
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 59. LED Configuration Register - Address 20, Hex 14 (Sheet Bit Name LED3 20.7:4 Programming bits 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = Read /Write Read Only Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. ...
Page 103
... Reserved 1. R/W = Read /Write Read Only Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Name Description Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Name Description Write as ‘ ...
Page 104
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Table 62 lists transmit control bits. Table 62. Transmit Control Register - Address 30, Hex 1E Bit Name 30.15:13 Reserved 30.12 Transmit Low Power 30.11:10 Port Rise Time Control 30.9:0 Reserved 1. Values are approximations and may vary outside indicated values based upon implementation loading conditions ...
Page 105
... Part Number LXT971ABC - Commercial Temperature Range (0ºC to +70ºC) Part Number LXT971ABE - Extended Temperature Range (-40ºC to +85ºC) NOTE: The package figure is generic and used only to demonstrate package dimensions. (The figure does not show the same number of pins as for the Intel 0.20 (4X) 7.00 ± 0.20 2 ...
Page 106
... LXT971A Single-Port 10/100 Mbps PHY Transceiver ® Figure 44. Intel LXT971A Transceiver LQFP Package Specifications 64-Pin Low-Profile Quad Flat Pack NOTE: The package figure is generic and used only to demonstrate package dimensions. (The figure does not show the same number of pins as for the Intel Millimeters Dim Min Max A – ...
Page 107
... Figure 45. Sample LQFP Package - Intel Pin 1 Figure 46 shows a sample Pb-Free (RoHS-compliant) LQFP package for the LXT971A Transceiver. Figure 46. Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel Pin 1 Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® ...
Page 108
... Figure 47. Sample TPBGA Package - Intel Pin 1 Figure 48 shows a sample Pb-Free (RoHS-Compliant) TPBGA package for the LXT971A Transceiver. Figure 48. Sample Pb-Free (RoHS Compliant) TPBGA Package - Intel Pin 1 108 ® LXT971A Transceiver LXT971ABC A4 ...
Page 109
... LXT971A Transceiver. Table 63. Product Ordering Information Number DJLXT971ALC.A4 DJLXT971ALE.A4 WJLXT971ALC.A4 WJLXT971ALE.A4 FLLXT971ABC.A4 FLLXT971ABE.A4 ELLXT971ABC.A4 ELLXT971ABE.A4 Datasheet Document Number: 249414-003 Revision Date: June 18, 2004 ® Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Package Revision Pin Count Type ...
Page 110
... Intel LXT971A Single-Port 10/100 Mbps PHY Transceiver Figure 49 shows an order matrix with sample information for ordering an LXT971A Transceiver. Figure 49. Order Matrix for Intel DJ LXT 110 ® LXT971A Transceiver - Sample 971A Product Revision Alphanumeric characters Temperature Range Ambient (0 – Commercial (0 – 70 ...