ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 56

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
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®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT971A Transceiver always transmits link pulses.
Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being
received. If this condition occurs, the LXT971A Transceiver returns to the auto-negotiation phase
if auto-negotiation is enabled. If the Link Integrity Test function is disabled by setting
Configuration Register bit 16.14 to ‘1’, the LXT971A Transceiver transmits packets, regardless of
link status.
10BASE-T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT971A
Transceiver. To enable this function, set Register bit 16.9 = 1. When this function is enabled, the
LXT971A Transceiver asserts its COL output for 5 to 15 bit times (BT) after each packet.
10BASE-T Jabber
If a transmission exceeds the jabber timer, the LXT971A Transceiver disables the transmit and
loopback functions. For jabber timing parameters, see
10BASE-T Jabber and Unjabber Timing” on page
The LXT971A Transceiver automatically exits jabber mode after the unjabber time has expired.
This function can be disabled by setting Register bit 16.10 = 1.
10BASE-T Polarity Correction
The LXT971A Transceiver automatically detects and corrects for the condition in which the
receive signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses, or
four inverted end-of-frame (EOF) markers, are received consecutively. If link pulses or data are not
received by the maximum receive time-out period (96 to 128 ms), the polarity state is reset to a
non-inverted state.
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•
If the Link Integrity Test function is enabled (the normal configuration), the LXT971A
Transceiver monitors the connection for link pulses. Once link pulses are detected, data
transmission is enabled and remains enabled as long as either the link pulses or data
transmission continue. If the link pulses stop, the data transmission is disabled.
If the Link Integrity Test function is disabled (which can be done by setting Configuration
Register bit 16.14 to ‘1’), the LXT971A Transceiver transmits to the connection regardless of
detected link pulses.
82.
Figure 34, “Intel® LXT971A Transceiver
Document Number: 249414-003
Revision Date: June 18, 2004
Datasheet