ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 94

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
94
Table 51. Auto-Negotiation Expansion - Address 6, Hex 6
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Table 51
1. RO = Read Only LH = Latching High
6.15:6
Bit
6.5
6.4
6.3
6.2
6.1
6.0
lists auto-negotiation expansion bits.
Reserved
Base Page
Parallel
Detection Fault
Link Partner
Next Page Able
Next Page Able
Page Received
Link Partner A/N
Able
Name
Ignore when read.
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is used only if Register bit
16.1 (that is, Alternate NP feature) is set.
0 = Base page = False (base page not received)
1 = Base page = True (base page received)
0 = Parallel detection fault has not occurred.
1 = Parallel detection fault has occurred.
0 = Link partner is not next page able.
1 = Link partner is next page able.
0 = Local device is not next page able.
1 = Local device is next page able.
This bit is cleared on Read. If Register bit 16.1 is set,
the Page Received bit is also cleared when either
mr_page_rx = false or transmit_disable = true.
1 = Indicates a new page is received and the received
0 = Link partner is not auto-negotiation able.
1 = Link partner is auto-negotiation able.
code word is loaded into Register 5 (Base Pages)
or Register 8 (Next Pages) as specified in Clause
28 of IEEE 802.3.
Description
Document Number: 249414-003
Revision Date: June 18, 2004
RO/LH
RO/LH
RO/LH
Type
RO
RO
RO
RO
1
Datasheet
Default
0
0
0
0
1
0
0