ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 8

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
Revision History
8
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
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Front page text changed.
Changed "PECL Interface" to "LVPECL Interface” in
Replaced text under
Modified first paragraph under
Modified text and added a new bullet in first and second set of bullets under
Interface”.
Replaced
Replaced
Added
Modified
Table 63 “Product Ordering Information”
Transceiver -
Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V.
Front Page: Changed “pseudo-ECL (PECL)” to “Low Voltage PECL (LVPECL).
Added “JTAG Boundary Scan” to Product Features on front page.
Modified
Modified
Modified
Added note under
function pins be tied to the inactive states and all outputs be left floating, if unused.”
Modified SD/TP description in
Added Table note 2.
Modified
Modified
Added
Replaced second paragraph under
Added
Changed “Far-End Fault” title to
Modified first sentence under this heading.
Modified
Added paragraph after bullets under
Modified text under
Modified
Section 10.1, “Top Label Markings”.
Table 8 “LXT971A Pin Types and
Section 3.2.2.1, “Increased MII Drive
Section 11.0, “Product Ordering Information”:
Figure 2 “LXT971A 64-Ball PBGA Assignments”
Figure 3 “LXT971A 64-Pin LQFP Assignments”
Table 1 “LQFP Numeric Pin List”
Table 4 “LXT971A Miscellaneous Signal
Table 5 “LXT971A Power Supply Signal
Figure 8 “Hardware Configuration
Table 13 “Supported JTAG
Figure 27 “Recommended LXT971A-to-3.3 V Fiber Transceiver Interface
Figure 28 “Recommended LXT971A-to-5 V Fiber Transceiver Interface
Sample”.
Intel
®
Section 2.0, “Signal
Section 3.7.3.4, “Fiber PMD
LXT971A Transceiver Revision 002 (Sheet 1 of 2)
Section 5.7.3.4, “Fiber PMD
Intel
®
Revision Date: August 6, 2002
LXT971A Transceiver Revision 003
Revision Date: 25-Oct-2005
Table 3 “LXT971A Network Interface Signal
Section 6.3, “The Fiber
‘100BASE-FX Far-End
Section 3.2.1.2, “Fiber
Instructions”.
Section 3.6.7.2, “Test
Descriptions”: “Intel recommends that all inputs and multi-
and changed
Modes”.
(replaced TEST1 and TEST0 with GND).
Description
Description
Settings”.
Strength”.
Sublayer”.
Descriptions”.
Sublayer”.
Descriptions”.
Figure 21 “Protocol
Figure 49 “Order Matrix for Intel® LXT971A
Interface”.
added RoHS information to
Fault”.
(replaced TEST1 and TEST0 with GND).
(replaced TEST1 and TEST0 with GND).
Interface”.
Loopback”.
Document Number: 249414-003
Sublayers”.
Descriptions”.
Revision Date: 25-Oct-2005
Section 6.3, “The Fiber
Circuitry”.
Circuitry”.
Datasheet