WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 17

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
Table 5
Cortina Systems
LXT972M: MII Data Interface Signal Descriptions
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
LQFP
Pin#
47
46
45
44
43
42
33
34
35
36
37
41
40
48
1
RX_CLK
TX_CLK
Symbol
TX_EN
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
TXD3
TXD2
TXD1
TXD0
COL
CRS
Type
O
O
O
O
O
O
O
I
I
Transmit Data.
TXD is a group of parallel data signals that are driven by the MAC.
TXD[3:0] transition synchronously with respect to TX_CLK.
TXD[0] is the least-significant bit.
Transmit Enable.
The MAC asserts this signal when it drives valid data on TXD.
This signal must be synchronized to TX_CLK.
Transmit Clock.
TX_CLK is sourced by the PHY in both 10 and 100 Mbps operations.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Receive Data.
RXD is a group of parallel signals that transition synchronously with
respect to RX_CLK.
RXD[0] is the least-significant bit.
Receive Data Valid.
The LXT972M PHY asserts this signal when it drives valid data on RXD.
This output is synchronous to RX_CLK.
Receive Error.
Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
Receive Clock.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
For details, see
Functional Description section.
Collision Detected.
The LXT972M PHY asserts this output when a collision is detected.
This output remains High for the duration of the collision.
This signal is asynchronous and is inactive during full- duplex operation.
Carrier Sense.
During half-duplex operation (register bit 0.8 = 0), the LXT972M PHY
asserts this output when either transmitting or receiving data packets.
During full-duplex operation (register bit 0.8 = 1), CRS is asserted only
during receive.
CRS assertion is asynchronous with respect to RX_CLK. CRS is de-
asserted on loss of carrier, synchronous to RX_CLK.
Section 5.3.2, Clock Requirements, on page 25
Signal Description
4.0 Signal Descriptions
in the
Page 17