WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 25

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.2.3.2
5.3
5.3.1
Notes:
5.3.2
5.3.2.1
5.3.2.2
5.4
Cortina Systems
Hardware Control Interface
The LXT972M PHY provides a Hardware Control Interface for applications where the
MDIO is not desired. The Hardware Control Interface uses the hardware configuration
pins to set device configuration.
Settings, on page 28.
Operating Requirements
Power Requirements
The LXT972M PHY requires three power supply inputs:
The digital and analog circuits require 3.3 V supplies (VCCA and VCCD). These inputs
may be supplied from a single source. Each supply input must be de-coupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either 2.5 V or
3.3 V. Also, the inputs on the MII interface are tolerant to 5 V signals from the controller on
the other side of the MII interface. For MII I/O characteristics, see
Characteristics
Clock Requirements
External Crystal/Oscillator
The LXT972M PHY requires a reference clock input that is used to generate transmit
signals and recover receive signals. It may be provided by either of two methods: by
connecting a crystal across the oscillator pins (XI and XO) with load capacitors, or by
connecting an external clock source to pin XI.
The connection of a clock source to the XI pin requires the XO pin to be left open. To
minimize transmit jitter, Cortina recommends a crystal-based clock instead of a derived
clock (that is, a PLL-based clock).
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather
than a crystal, is frequently used in switch applications. For clock timing requirements, see
Table 25, I/O Characteristics - REFCLK/XI and XO Pins, on page
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data
clock (MDC) speed is a maximum of 8 MHz.
Initialization
This section includes the following topics:
®
1. Bring up power supplies as close to the same time as possible.
2. As a matter of good practice, keep power supplies as clean as possible.
• VCCA
• VCCD
• VCCIO
•
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Section 5.4.1, MDIO Control Mode and Hardware Control Mode
1
- MII Pins, on page
For details, see Section 5.4.4, Hardware Configuration
52.
5.3 Operating Requirements
53.
Table 24, Digital I/O
Page 25