WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 41

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.7.3.2.3
5.7.3.2.4
5.7.3.3
5.7.3.3.1
5.7.3.3.2
5.7.3.3.3
Cortina Systems
Carrier Sense
For 100BASE-TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes
assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair
causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are
received without /T/R. However, in this case RX_ER is asserted for one clock cycle when
CRS is de-asserted.
Cortina does not recommend using CRS for Interframe Gap (IFG) timing for the following
reasons:
Receive Data Valid
The LXT972M PHY asserts RX_DV to indicate that the received data maps to valid
symbols. In 100 Mbps operation, RX_DV is active with the first nibble of preamble.
Twisted-Pair Physical Medium Dependent Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides signal scrambling and
de-scrambling functions, line coding and decoding functions (MLT-3 for 100BASE-TX,
Manchester for 10BASE-T), as well as receiving, polarity correction, and baseline wander
correction functions.
Scrambler/Descrambler
The purpose of the scrambler/descrambler is to spread the signal power spectrum and
further reduce EMI using an 11-bit, data-independent polynomial. The receiver
automatically decodes the polynomial whenever IDLE symbols are received.
Scrambler Seeding. Once the transmit data (or Idle symbols) are properly encoded, they
are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit
scrambler seed. Five seed bits are determined by the PHY address, and the remaining
bits are hard coded in the design.
Scrambler Bypass. The scrambler/de-scrambler can be bypassed by setting register bit
16.12 = 1. Scrambler bypass is provided for diagnostic and test support.
Polarity Correction
The 100 Mbps twisted pair signaling is not polarity sensitive. As a result, the polarity
status is not a valid status indicator.
Baseline Wander Correction
The LXT972M PHY provides a baseline wander correction function for when the
LXT972M PHY is under network operating conditions. The MLT3 coding scheme used in
100BASE-TX is by definition “unbalanced”. As a result, the average value of the signal
voltage can “wander” significantly over short time intervals (tenths of seconds). This
wander can cause receiver errors at long-line lengths (100 meters) in less robust designs.
Exact characteristics of the wander are completely data dependent.
The LXT972M PHY baseline wander correction characteristics allow the device to recover
error-free data while receiving worst-case packets over all cable lengths.
®
• CRS de-assertion time is slightly longer than CRS assertion time. As a result, an IFG
• CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in
LXT972M Single-Port 10/100 Mbps PHY Transceiver
interval appears somewhat shorter to the MAC than it actually is on the wire.
half-duplex mode.
5.7 100 Mbps Operation
Page 41