WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 72

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
9.0
Table 49
Table 50
Cortina Systems
Register Definitions - Product-Specific Registers
This chapter includes definitions of product-specific LXT972M PHY registers that are
defined in accordance with the IEEE 802.3 standard for adding unique device functions.
(For definitions of the IEEE base registers used by the LXT972M PHY, see
Register Definitions - IEEE Base Registers
Register Set for Product-Specific Registers
Configuration Register - Address 16, Hex 10 (Sheet 1 of 2)
®
1. R/W = Read /Write
16.15
16.14
16.13
16.12
16.10
16.11
Address
•
•
16.9
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Bit
22-25
Table 49
Table 50
(address 17 through 30).
16
17
18
19
20
21
26
27
28
29
30
31
Reserved
Jabber
(10BASE-T)
SQE
(10BASE-T)
Reserved
Force Link Pass
Transmit Disable
Bypass Scrambler
(100BASE-TX)
Port Configuration Register
Status Register #2
Interrupt Enable Register
Status Change Register
LED Configuration Register
Reserved
Reserved
Digital Configuration Register
Reserved
Reserved
Reserved
Transmit Control Register
Reserved
lists the register set of the product-specific registers.
through
Name
Table 56
Write as ‘0’. Ignore on Read.
0 = Normal operation
1 = Force Link pass
0 = Normal operation
1 = Disable Twisted Pair transmitter
0 = Normal operation
1 = Bypass Scrambler and Descrambler
Write as ‘0’. Ignore on Read.
0 = Normal operation
1 = Disable Jabber Correction
0 = Disable Heart Beat
1 = Enable Heart Beat
Register Name
provide bit descriptions of the product-specific registers
.)
Description
See
See
See
See
See
—
—
See
—
—
—
See
—
Product-Specific Registers
9.0 Register Definitions -
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Bit Assignments
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Section 8.0,
1
Default
Page 72
0
0
0
0
0
0
0