LPC1833FET256,551 NXP Semiconductors, LPC1833FET256,551 Datasheet - Page 37

• Manufacturer Part Number: LPC1833FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1833FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293791551

NXP Semiconductors
1.
LPC1850_30_20_10
Objective data sheet
The encryption function is not available on standard LPC18xx parts. Please contact your local distributor or the NXP sales office for
availability of encryption-capable parts.
7.10.1.1 Features
7.10.1 AES security engine
7.10.2 One-Time Programmable (OTP) memory
7.11.1 Features
7.10 Security features
7.11 General Purpose I/O (GPIO)
The hardware AES security engine can encrypt
algorithm in conjunction with a 128-bit key.
The OTP provides two 128-bit non-volatile memories to store AES keys or other customer
data.
The LPC1850/30/20/10 provides 5 GPIO ports with up to 16 GPIO pins each.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
All GPIO pins default to inputs with pull-up resistors enabled on reset.
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Decryption of external flash data connected to the quad SPI Flash Interface (SPIFI).
Secure storage of keys.
Support for CMAC hash calculation to authenticate encrypted data.
Data is processed in little endian mode. This means that the first byte read from flash
is integrated into the AES codeword as least significant byte. The 16th byte read from
flash is the most significant byte of the first AES codeword.
AES engine performance of 1 byte/clock cycle.
DMA transfers supported through the GPDMA.
Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
– Mask registers allow treating sets of port bits as a group, leaving other bits
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
be achieved.
unchanged.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 17 February 2011
1
32-bit ARM Cortex-M3 microcontroller
and decrypt data using the AES
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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