LPC1833FET256,551 NXP Semiconductors, LPC1833FET256,551 Datasheet - Page 46

• Manufacturer Part Number: LPC1833FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1833FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293791551

NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
7.13.6.1 Features
7.14.1.1 Features
7.13.6 C_CAN
7.14.1 General purpose 32-bit timers/external event counters
7.14 Counter/timers and motor control
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
The LPC1850/30/20/10 include four 32-bit timer/counters. The timer/counter is designed
to count cycles of the system derived clock or an externally-supplied clock. It can
optionally generate interrupts, generate timed DMA requests, or perform other actions at
specified timer values, based on four match registers. Each timer/counter also includes
two capture inputs to trap the timer value when an input signal transitions, optionally
generating an interrupt.
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Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
Provides programmable loop-back mode for self-test operation.
A 32-bit timer/counter with a programmable 32-bit prescaler.
Counter or timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 17 February 2011
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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