HMP8156ACNZ Intersil, HMP8156ACNZ Datasheet - Page 11

• Manufacturer Part Number: HMP8156ACNZ
• Description: IC VIDEO ENCODER NTSC/PAL 64MQFP
• Manufacturer: Intersil
• Type: NTSC/PAL Encoderr

Specifications of HMP8156ACNZ

• Applications: Multimedia, Video Editing
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-Bit BT.656 Format
When BT.656 format is selected, data is latched on each
rising edge of CLK2. Overlay data is latched when the Y
input data is latched. However, the overlay data must arrive
three pixels after its corresponding Y data. The pixel and
overlay input timing is shown in Figure 12.
As inputs, the BLANK, HSYNC, and VSYNC pins are
ignored since all timing is derived from the EAV and SAV
sequences within the data stream. As outputs, BLANK,
HSYNC and VSYNC are output following the rising edge of
CLK2. If the CLK pin is configured as an input, it is ignored. If
configured as an output, it is one-half the CLK2 frequency.
Square pixel operation, overlay processing with internal
mixing, flicker filtering, and SIF mode 2X upsampling are not
supported for the BT.656 input format. Also, the HSYNC,
VSYNC, and BLANK signals must be configured as outputs.
Video Timing Control
Regardless of the input mode, the output video timing of the
HMP8154/HMP8156A is at 50 or 59.94 fields per second
(interlaced). For normal and 2X upscaling modes, the pixel
input timing is at 50 or 59.94 fields per second; with the
flicker filter enabled, the input timing rate is twice as fast.
The output video and pixel input timing is controlled by the
BLANK, HSYNC, VSYNC, FIELD, and CLK2 pins.
HSYNC, VSYNC, and Field Timing
The leading edge of HSYNC indicates the beginning of a
horizontal sync interval. If HSYNC is an output, it is asserted
for about 4.7μs. If HSYNC is an input, it must be active for at
least two CLK2 periods. The width of the horizontal
composite sync tip is determined from the video standard
and does not depend on the width of HSYNC.
The leading edge of VSYNC indicates the beginning of a
vertical sync interval. If VSYNC is an output, it is asserted for
3 scan lines in (M, NSM) NTSC and (M, N) PAL modes or
2.5 scan lines in (B, D, G, H, I, CN) PAL modes. If VSYNC is
an input, it must be asserted for at least two CLK2 periods.
When HSYNC and VSYNC are configured as outputs, their
leading edges will occur simultaneously at the start of an odd
(OUTPUT)
OL0-OL2,
BLANK
P8-P15
M1, M0
CLK2
Cb 2
Y 2
11
Cr 2
PIXEL 0
FIGURE 12. PIXEL AND OVERLAY INPUT TIMING - BT.656
Y 3
Cb 4
HMP8154, HMP8156A
PIXEL 1
Y 4
field. At the start of an even field, the leading edge of
VSYNC occurs in the middle of the line.
When HSYNC and VSYNC are configured as inputs, the
HMP8154/HMP8156A provides a programmable HSYNC
window for determining FIELD. The window is specified with
respect to the leading or trailing edge of VSYNC. The edge
is selected in the field control register. When HSYNC is
found inside the window, then the encoder sets FIELD to the
value specified in the field control register.
The HMP8154/HMP8156A provides programmable timing
for the VSYNC input. At the active edge of VSYNC, the
encoder resets its vertical half-line counter to the value
specified by the field control register. This allows the input
and output syncs to be offset, although the data must still be
aligned.
The FIELD signal is always an output and changes state
near each leading edge of VSYNC. The delay between the
syncs and FIELD depends on the encoder’s operating mode
as summarized in Table 6. In modes in which the encoder
uses CLK to gate its inputs and outputs, the FIELD signal
may be delayed 0-12 additional CLK2 periods.
Figure 13 illustrates the HSYNC, VSYNC, and FIELD
general timing for (M, NSM) NTSC and (M, N) PAL. Figure
14 illustrates the general timing for (B, D, G, H, I, CN) PAL. In
the figures, all the signals are shown active low (their reset
state), and FIELD is low during odd fields.
DIRECTION
"FF"
SYNC I/O
PIXEL N-2
Output
OPERATING MODE
Input
Input
"00"
DIRECTION
TABLE 6. FIELD OUTPUT TIMING
BLANK I/O
Don’t Care
Output
Input
"00"
PIXEL N-1
"XY"
DELAY
CLK2
148
138
32
"10"
FIELD lags VSYNC
switching from odd to even.
FIELD lags the earlier of
VSYNC and HSYNC when
syncs are aligned when
switching from even to odd.
FIELD lags VSYNC.
FIELD leads VSYNC.
PIXEL N
"80"
COMMENTS
August 20, 2009
"10"
FN4343.5