HMP8156ACNZ Intersil, HMP8156ACNZ Datasheet - Page 23

• Manufacturer Part Number: HMP8156ACNZ
• Description: IC VIDEO ENCODER NTSC/PAL 64MQFP
• Manufacturer: Intersil
• Type: NTSC/PAL Encoderr

Specifications of HMP8156ACNZ

• Applications: Multimedia, Video Editing
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
7-1
7-0
7-0
7-4
0
2
1
0
Reserved
Assert BLANK
Output Signal
(Vertical)
Negate BLANK
Output Signal
(Vertical)
Field Detect
Window Size Low
Half Line Count
Reset Value
VSYNC Edge
Select
FIELD Detect
Select
Field Detect
Window Size High
FUNCTION
FUNCTION
FUNCTION
FUNCTION
23
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start inputting pixel
input data each noninterlaced input frame. The output video will be active starting on line
number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1X clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = leading edge
1 = trailing edge
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = odd field
1 = even field
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size
value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
TABLE 27. START V_BLANK HIGH REGISTER
TABLE 29. FIELD CONTROL REGISTER 1
TABLE 30. FIELD CONTROL REGISTER 2
TABLE 28. END V_BLANK REGISTER
HMP8154, HMP8156A
SUB ADDRESS = 24
SUB ADDRESS = 25
SUB ADDRESS = 26
SUB ADDRESS = 27
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
(note that this does not
August 20, 2009
0000000
RESET
RESET
RESET
RESET
00000
STATE
STATE
STATE
STATE
13
80
1
0
0
0
FN4343.5
B
B
B
B
H
H
B
B