PCA9506DGG,518 NXP Semiconductors, PCA9506DGG,518 Datasheet

IC I/O EXPANDER I2C 40B 56TSSOP

PCA9506DGG,518

Manufacturer Part Number
PCA9506DGG,518
Description
IC I/O EXPANDER I2C 40B 56TSSOP
Manufacturer
NXP Semiconductors
Datasheets

Specifications of PCA9506DGG,518

Package / Case
56-TSSOP
Interface
I²C
Number Of I /o
40
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9506
Number Of Lines (input / Output)
40.0 / 40.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
500 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5.5 V
Logic Type
I/O Expander
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
40.0
Number Of Output Lines
40.0
Output Current
50 mA
Output Voltage
5.5 V
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
TSSOP
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935280798518
PCA9506DGG-T
PCA9506DGG-T
1. General description
2. Features
The PCA9506 provides 40-bit parallel input/output (I/O) port expansion for I
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 800 mA to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. Output
ports are totem-pole and their logic state changes at the Acknowledge (bank change).
The device can be configured to have each input port to be masked in order to prevent it
from generating interrupts when its state changes and to have the I/O data logic state to
be inverted when read by the system master.
An open-drain interrupt (INT) output pin allows monitoring of the input pins and is
asserted each time a change occurs in one or several input ports (unless masked).
The Output Enable (OE) pin 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os
as inputs. Three address select pins configure one of 8 slave addresses.
The PCA9506 is available in 56-pin TSSOP and HVQFN packages and is specified over
the 40 C to +85 C industrial temperature range.
PCA9506
40-bit I
Rev. 01 — 14 February 2006
Standard mode (100 kHz) and Fast mode (400 kHz) compatible I
interface
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
40 configurable I/O pins that default to inputs at power-up
Outputs:
Inputs:
Active LOW reset (RESET) input pin resets device to power-up default state
3 programmable address pins allowing 8 devices on the same bus
Totem-pole (10 mA source, 25 mA sink) with controlled edge rate output structure
Active LOW output enable (OE) input pin 3-states all outputs
Output state change on Acknowledge
Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change
Polarity Inversion register allows inversion of the polarity of the I/O pins when read
2
C-bus I/O port with RESET, OE, and INT
Product data sheet
2
C-bus serial
2
C-bus

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PCA9506DGG,518 Summary of contents

Page 1

PCA9506 40-bit I Rev. 01 — 14 February 2006 1. General description The PCA9506 provides 40-bit parallel input/output (I/O) port expansion for I applications organized in 5 banks of 8 I/Os supply voltage, the outputs are capable ...

Page 2

Philips Semiconductors Designed for live insertion Minimize line disturbance (I Signal transient rejection (50 ns noise filter and robust I Low standby current +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM ...

Page 3

Philips Semiconductors 5. Block diagram SCL SDA RESET Fig 1. Block diagram of PCA9506 9397 750 14939 Product data sheet 40-bit I PCA9506 LOW PASS INPUT FILTERS POWER-ON RESET All I/Os are set ...

Page 4

Philips Semiconductors write configuration Fig 2. Simplified schematic of IO0_0 to IO4_7 9397 750 14939 Product data sheet 40-bit I I/O configuration register data from D Q shift register CK Q pulse data from D Q shift register write pulse ...

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Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for TSSOP56 9397 750 14939 Product data sheet 2 40-bit I C-bus I/O port with RESET, OE, and INT 1 SDA SCL 2 IO0_0 3 4 IO0_1 5 IO0_2 ...

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Philips Semiconductors Fig 4. Pin configuration for HVQFN56 6.2 Pin description Table 2: Symbol SDA SCL IO0_0 to IO0_7 IO1_0 to IO1_7 IO2_0 to IO2_7 IO3_0 to IO3_7 IO4_0 to IO4_7 9397 750 ...

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Philips Semiconductors Table 2: Symbol OE INT RESET [1] HVQFN package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs ...

Page 8

Philips Semiconductors The lowest 6 bits are used as a pointer to determine which register will be accessed. The registers are: • IP: Input Port registers (5 registers) • OP: Output Port registers (5 registers) • PI: Polarity Inversion registers ...

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Philips Semiconductors 7.3 Register definitions Table 3: Register summary Register # (hex) Input Port registers ...

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Philips Semiconductors Table 3: Register summary …continued Register # (hex) Mask Interrupt registers ...

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Philips Semiconductors 7.3.2 OP0 to OP4 - Output Port registers These registers reflect the outgoing logic levels of the pins defined as outputs by the I/O Configuration register. Bit values in these registers have no effect on pins defined as ...

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Philips Semiconductors 7.3.4 IOC0 to IOC4 - I/O Configuration registers These registers configure the direction of the I/O pins. Cx[ The corresponding port pin is an output. Cx[ The corresponding port pin is an input. Where ...

Page 13

Philips Semiconductors 7.6 Interrupt output (INT) The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt not masked. The interrupt ...

Page 14

Philips Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...

Page 15

Philips Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed ...

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SDA output bank START condition register bank 0 R selected acknowledge from slave acknowledge ...

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SDA START condition R acknowledge from slave The programming becomes effective at the acknowledge. Less ...

Page 18

Philips Semiconductors 9. Application design-in information V DD 1 (optional) MASTER CONTROLLER SCL SDA RESET INT OE GND Device address configured as 0100 000X for this example. IO0_0, IO0_2, IO0_3, IO1_0 to IO3_7 are configured ...

Page 19

Philips Semiconductors 10. Limiting values Table 9: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I I input current I V input/output voltage on any other pin ...

Page 20

Philips Semiconductors Table 10: Static characteristics Symbol Parameter I/Os V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I total ...

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Philips Semiconductors 12. Dynamic characteristics Table 11: Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START HD;STA condition t set-up time for a repeated ...

Page 22

Philips Semiconductors [5] The maximum t for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f 250 ns. This allows series protection resistors to be connected between ...

Page 23

Philips Semiconductors START SCL SDA RESET rec(rst) IOx_y Fig 18. Reset timing 13. Test information Fig 19. Test circuitry for switching times 9397 750 14939 Product data sheet 40-bit PULSE GENERATOR R ...

Page 24

Philips Semiconductors 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. ...

Page 25

Philips Semiconductors HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 0.85 mm terminal 1 index area terminal 1 56 index area DIMENSIONS (mm are ...

Page 26

Philips Semiconductors 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However totally safe desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 ...

Page 27

Philips Semiconductors • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to ...

Page 28

Philips Semiconductors [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may ...

Page 29

Philips Semiconductors 19. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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