PCA9506DGG,518 NXP Semiconductors, PCA9506DGG,518 Datasheet - Page 22

• Manufacturer Part Number: PCA9506DGG,518
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9506DGG,518

• Package / Case: 56-TSSOP
• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9506
• Number Of Lines (input / Output): 40.0 / 40.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 40.0
• Number Of Output Lines: 40.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: TSSOP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935280798518; PCA9506DGG-T; PCA9506DGG-T

Philips Semiconductors
[5]
[6]
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9397 750 14939
Product data sheet
Fig 16. Definition of timing on the I
Fig 17. I
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
b
SDA
SCL
= total capacitance of one bus line in pF.
Rise and fall times refer to V
2
C-bus timing diagram
P
t
BUF
protocol
SDA
f
SCL
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
S
t
SU;STA
t
t
HD;STA
BUF
condition
t
LOW
START
(S)
t
HD;STA
IL
f
.
and V
2
C-bus
t
t
t
LOW
r
HD;DAT
t
r
IH
.
MSB
bit 7
(A7)
t
HIGH
Rev. 01 — 14 February 2006
t
t
HIGH
SU;DAT
t
f
1
/f
bit 6
(A6)
SCL
t
f
t
HD;DAT
t
SU;DAT
40-bit I
(R/W)
bit 0
t
VD;DAT
2
acknowledge
C-bus I/O port with RESET, OE, and INT
Sr
(A)
t
SU;STA
t
HD;STA
t
VD;ACK
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
condition
STOP
(P)
t
SU;STO
002aab175
t
SP
t
SU;STO
PCA9506
002aaa986
f
is specified at
P
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