PCA9518AD,118 NXP Semiconductors, PCA9518AD,118 Datasheet - Page 7

• Manufacturer Part Number: PCA9518AD,118
• Description: IC I2C BUS HUB 5-CH 20SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9518AD,118

• Package / Case: 20-SOIC (7.5mm Width)
• Applications: CMOS Bus Controller
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Logic Family: PCA9518A
• Operating Supply Voltage: 2.3 V to 3.6 V
• Power Dissipation: 300 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C Bus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935284253118; PCA9518AD-T; PCA9518AD-T

NXP Semiconductors
PCA9518A_3
Product data sheet
Fig 5.
SUBSYSTEM 5
SUBSYSTEM 6
not connected
100 kHz
400 kHz
disabled;
Only two of the five channels on the PCA9518A Device 2 are being used. EN3 and EN4 are connected to V
channels 3 and 4 and/or SDA3/SCL3 and SDA4/SCL4 are pulled up to V
port, but if unused then it must be pulled up to V
The pull-ups shown on Device 2 channels 3 and 4 are not required if their enable pins (ENn) are permanently held LOW.
Typical application: multiple expandable 5-channel I
SDA
SDA
SCL
SCL
3.3 V
5 V
or 5 V
or 5 V
3.3 V
3.3 V
In order to illustrate what would be seen in a typical application, refer to
bus master in
the waveform shown in
the small foot preceding each clock LOW-to-HIGH transition and proceeding each data
LOW-to-HIGH transition for the master. The foot height is the difference between the LOW
level driven by the master and the higher voltage LOW level driven by the PCA9518A
repeater. Its width corresponds to an effective clock stretching coming from the
PCA9518A that delays the rising edge of the clock. That same magnitude of delay is seen
on the rising edge of the data. The foot on the rising edge of the data is extended through
the 9
master. The clock of the slave looks normal except the V
by the PCA9518A. The SDA at the slave has a particularly interesting shape during the 9
clock cycle where the slave pulls the line below the value driven by the PCA9518A during
SDA1
SCL1
SDA2
SCL2
SDA3
SCL3
SDA4
SCL4
PCA9518A
th
DEVICE 2
clock pulse as the PCA9518A repeats the acknowledge from the slave to the
V
V
DD
EXPSDA1
EXPSDA2
SS
EXPSCL1
EXPSCL2
SDA0
SCL0
EN1
EN2
EN3
EN4
Figure 5
Rev. 03 — 3 December 2008
were to write to the slave through the PCA9518A, we would see
Figure
3.3 V
DD
since there is no enable pin.
6. This looks like a normal I
MASTER
400 kHz
BUS
SDA
SCL
2
C-bus hubs
DD
. SDA0 and SCL0 can be used as a normal I
EXPSDA1
EXPSDA2
EXPSCL1
EXPSCL2
SDA0
SCL0
EN1
EN2
EN3
EN4
Expandable 5-channel I
PCA9518A
DEVICE 1
V
V
OL
DD
SS
2
C-bus transmission except for
is the ~0.5 V level generated
SDA1
SDA2
SDA3
SDA4
SCL1
SCL2
SCL3
SCL4
PCA9518A
3.3 V
3.3 V
5 V
5 V
© NXP B.V. 2008. All rights reserved.
Figure
SS
to disable
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SUBSYSTEM 1
SUBSYSTEM 2
SUBSYSTEM 3
SUBSYSTEM 4
2
C-bus hub
400 kHz
400 kHz
100 kHz
100 kHz
6. If the
002aac535
2
C-bus
7 of 23
th