PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 87

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

For transmit direction, contents of time slot 0 are additionally determined by the selected
transparent mode (see also
Table 20
enabled by
–
XSP.TT0
TSWM.TSIF
TSWM.TSIS
TSWM.TRA
TSWM.TSA4–8
1)
2)
3)
4)
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the 16 bit CRC Error Counter
CEC (one error per submultiframe, maximum).
Additionally a CRC4 error interrupt status ISR0.CRC4 may be generated if enabled by
IMR0.CRC4.
All CRC bits of one outgoing submultiframe are automatically inverted in case a CRC
error is flagged for the previous received submultiframe. This function is enabled via bit
RC0.CRCI. Setting the bit RC0.XCRCI inverts the CRC bits before transmission to the
distant end. The function of RC0.XCRCI and RC0.CRCI are logically ored.
4.4.3.1
Multiframe alignment is assumed to have been lost if doubleframe alignment has been
lost (flagged on status bit FRS0.LFA). The rising edge of this bits causes an interrupt.
The multiframe resynchronization procedure starts when doubleframe alignment has
been regained which is indicated by an interrupt status bit ISR2.FAR. For doubleframe
synchronization refer to section doubleframe format. It may also be invoked by the user
by setting
• bit FMR0.FRS for complete doubleframe and multiframe re-synchronization
• bit FMR1.MFCS for multiframe re-synchronization only.
The CRC checking mechanism is enabled after the first correct multiframe pattern has
been found. However, CRC errors are not counted in asynchronous state.
Data Sheet
pin XDI or XSIG or XFIFO buffer (signaling controller)
Automatic transmission of the A-bit is selectable
The S
Additionally, automatic transmission of submultiframe error indication is selectable
a
-bit register XSA4-8 may be used optionally
Synchronization Procedure
Transmit Transparent Mode (CRC Multiframe E1)
Framing +
CRC
(int. generated)
via pin XDI
via pin XDI
via pin XDI
(int. generated)
(int. generated)
Transmit Transparent Source for
1)
Figure
A Bit
XSW.XRA
via pin XDI
XSW.XRA
XSW.XRA
via pin XDI
XSW.XRA
25):
87
2)
1)
1)
1)
Sa Bits
XSW.XY0 … 4
via pin XDI
XSW.XY0 … 4
XSW.XY0 … 4
XSW.XY0 … 4
via pin XDI
Functional Description E1
3)
2)
2)
2)
E Bits
XSP.XS13/XS15
via pin XDI
(int. generated)
via pin XDI
XSP.XS13/XS15
XSP.XS13/XS15
FALC-LH V1.3
PEB 2255
2000-07
4)
3)
3)