UJA1023T/2R04,512 NXP Semiconductors, UJA1023T/2R04,512 Datasheet
UJA1023T/2R04,512
Specifications of UJA1023T/2R04,512
UJA1023T/2R04
UJA1023T/2R04
Related parts for UJA1023T/2R04,512
UJA1023T/2R04,512 Summary of contents
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UJA1023 LIN-I/O slave Rev. 5 — 17 August 2010 1. General description The UJA1023 is a stand-alone Local Interconnect Network (LIN) I/O slave that replaces basic components commonly used in electronic control units for input and output handling. The UJA1023 ...
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... NXP Semiconductors 2. Features and benefits Automatic bit rate synchronization to any (master) bit rate between 1 kbit/s and 20 kbit/s Integrated LIN 2.0 / SAE J2602 transceiver (including 30 kΩ termination resistor) Eight bidirectional I/O pins 4 × × × 4 switch matrix to support reading and supplying a maximum ...
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... NXP Semiconductors 4. Ordering information Table 2. Ordering information Type number Package Name [1] UJA1023T/2R04/C SO16 [1] UJA1023T/2R04 SO16 [ 5 for the UJA1023T/2R04/C; V BAT 5. Block diagram 3 BAT 5 GND TERMINATION 4 LIN LIN TRANSCEIVER OSCILLATOR CONFIGURATION Fig 1. Block diagram UJA1023 Product data sheet Description plastic small outline package; 16 leads; body width 3.9 mm plastic small outline package ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. Symbol VIO INH BAT LIN GND [ input output; I/O = input or output. UJA1023 Product data sheet VIO 1 2 INH BAT 3 4 LIN GND Pin configuration Pin description [1] Pin Type Description 1 I reference input for level adaptation of the I/O pins ...
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... NXP Semiconductors 7. Functional description The UJA1023 combines all blocks necessary to work as a stand-alone LIN slave. Various I/O functions typically used in a car are supported. For a more detailed description refer to Section 7.2 7.1 Short description of the UJA1023 7.1.1 LIN controller The LIN 2.0 controller monitors and evaluates the LIN messages in order to process the LIN commands ...
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... NXP Semiconductors 7.1.8 Cyclic sense To reduce current consumption, the cyclic sense function can be used to read a switch. The switch will be supplied and read back periodically. 7.2 LIN controller 7.2.1 Configuration In this data sheet basic knowledge of the “LIN diagnostic and configuration specification, Rev. 2.0” is expected. ...
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NAD (optional) MasterReq SlaveResp ID: 3C ID: 3D Fig 3. Typical configuration flow slave I/O configuration assign frame ID via data dump MasterReq SlaveResp MasterReq ID: 3C ID: 3D ID: 3C enable new I/O configuration PxResp SlaveResp configured RxReq ...
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... NXP Semiconductors 7.2.1.2 LIN slave node address assignment The default slave Node Address (NAD) after power-on depends on the input levels of the configuration pins C1, C2 and C3. These pins will be sampled directly after the power-on event. The relation between the configuration pins and the NAD is shown in Table 4 ...
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... NXP Semiconductors Table 6. Byte and and The format of the positive response is shown in Table 7. Data byte [ different values possible; see The NAD assignment can be done via Daisy Chain (DC), (see assignment”) as well as via Plug ID (see NAD assignment can be distinguished on the value of the initial NAD, which is the first data byte D0 of the MasterReq assign NAD request ...
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... NXP Semiconductors Daisy chain NAD assignment: frame and the type of configuration is daisy chain, the following actions can take place, depending on the initial NAD value: • Initial NAD 0x20: Daisy chain on, the pin drivers are enabled • Initial NAD 0x21: The input level on the configuration pin C1 and the status flag of the internal DC-switch is read ...
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CONFIGURED UJA1023 MASTER ASSIGN NAD INITIAL NAD = DAISY CHAIN DC FLAG BAT BAT LIN GND BAT LIN C1 PLUG PLUG BAT GND Fig 4. Daisy chain ID IN CONFIGURATION 1 UJA1023 ASSIGN NAD INITIAL NAD = DAISY CHAIN BAT ...
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... NXP Semiconductors Plug ID NAD assignment: C3. Once the assign NAD MasterReq with the initial NAD ‘Plug ID configuration’ is received, the UJA1023 compares the values of the configuration pins C3, C2, and C1 with the values of the data bits D0[2:0]. If the values are equal and bits D0[7:4] are logic 0 and D0[3] is logic 1, the value used as new NAD for the UJA1023. Next, for example, the ‘ ...
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UJA1023 MASTER ASSIGN NAD INITIAL NAD DATA BYTE 7 D0.0 COMPARATOR BAT BAT GND C1 BAT LIN BAT LIN PLUG PLUG BAT GND Fig 5. Plug ID 1 UJA1023 ASSIGN ...
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... NXP Semiconductors 7.2.1.3 Assign frame ID By means of the assign frame ID command the LIN message identifier PxReq and PxResp can be changed to the desired values. Table 8. Data byte Table 9. Byte and D4 D5 and D6 D7 The format of the positive response is shown in Table 10. Data byte ...
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... NXP Semiconductors 7.2.1.4 Read by identifier It is possible to read the supplier identifier, function identifier and the variant of the UJA1023 by means of the read by identifier request. The format for this request is shown in Table in Table Table 11. Data byte Table 12. Byte and D5 D6 and D7 Table 13. ...
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... NXP Semiconductors Table 14. Data byte 7.2.1.5 I/O configuration The I/O configuration is done via the LIN configuration request ‘Data Dump’, where the first data byte of the MasterReq contains the slave node address NAD. The I/O-pin configuration process starts only, if the received slave node address matches the own UJA1023 node address and if data byte D2 (SID) is 0xB4 ...
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... NXP Semiconductors Table 16. Byte and UJA1023 Product data sheet First I/O configuration data block bit description Bit Symbol Description NAD[7:0] Slave node address (NAD). NAD values are in the range from 1 to 127, while 0 and 128 to 255 are reserved for other purposes. The slave node address is assigned with the ...
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... NXP Semiconductors The second configuration data block (shown in D3 Table 17. Second I/O configuration data block bit allocation Data 7 6 byte D0 NAD7 NAD6 CM0_7 CM0_6 D5 CM1_7 CM1_6 D6 TH2/TH1 TH2/TH1 D7 LWM7 LWM6 Table 18. Byte UJA1023 Product data sheet NAD5 NAD4 NAD3 LSLP TxDL ...
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... NXP Semiconductors Table 18. Byte D4 and Table 19 transmitter, selection between classic or enhanced checksum model, limp home output value and PWM initial value selected only if D3 and D3 Table 19. Data byte [ [ reserved, must be ‘0’. Table 20. Byte UJA1023 Product data sheet Second I/O configuration data block bit description ...
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... NXP Semiconductors Table 20. Byte and Table 21 used for I/O-pin configuration but to provide the master with diagnosis data of the UJA1023 read-only data block. If the slave node address matches and the fourth data block is selected, the UJA1023 transmits its diagnosis data via the SlaveResp message ...
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... NXP Semiconductors Table 23. Data byte [1] Undefined. Table 24. Byte [ and [1] All diagnosis flags in byte D4 are reset after data access from master. UJA1023 Product data sheet Fourth I/O diagnostic data block response frame bit allocation NAD7 NAD6 NAD5 NAD4 RxB CS TxB PL7 PL6 ...
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... NXP Semiconductors 7.2.1.6 Configuration examples Example 1, UJA1023 configuration with eight low-side outputs. // //Example 8 LSE and walking ‘1’ pattern //C1, C2 and C3 are GND //SB = SyncBreak SyncField // UJA1023 Product data sheet // Assign frameID, default NAD used and // ID(PxReq) = 04,ID(PxResp Positive response // Datadump1, 8 × LSE ...
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... NXP Semiconductors Example 2, UJA1023 configuration with eight inputs and edge capture. // //Example 8 inputs with capture //C1, C2 and C3 are GND //SB = SyncBreak SyncField // UJA1023 Product data sheet // Assign frameID, default NAD used and // ID(PxReq) = 04,ID(PxResp Positive response // Datadump1, all outputs disabled (optional) // Read back configuration sent ...
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... NXP Semiconductors 7.2.2 Operating modes Configuration Active mode HSE, LSE: 0x00 PxO: 0x00 INH: HIGH LIN: active default NAD used NAD reconfiguration HSE, LSE: 0×00 P×O: 0×00 Normal Active mode HSE: as configured LSE: as configured PxO: output data INH: as configured LIN: active ...
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... NXP Semiconductors 7.2.2.1 Configuration mode The Configuration mode can be seen as initial state after power-on or undervoltage detection. The UJA1023 configuration values are in the default settings. The I/O pins (Px) are set to high-impedance behavior and the INH is in its External regulator mode, which outputs a HIGH-level in order to switch on an external voltage regulator ...
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... NXP Semiconductors In LH sleep mode the PWM and ADC are reset. The first LIN message will be lost due to waking up the UJA1023. 7.2.2.5 Limp home mode and Standby mode Limp home mode and Standby mode differ in the output of pin INH if the INH is configured in External regulator mode ...
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... NXP Semiconductors The Cyclic sense mode can be configured via the Output mode bits OM0 and OM1 in the configuration data bytes (see TH3 will be used instead. This feature is used for diagnosis purposes to check the presence of a switch with an integrated parallel resistor (typical value is 2800 Ω ± 1 %). ...
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... NXP Semiconductors This means that the scan matrix value is determined directly after the previous LIN message. In case two or more switches are closed simultaneously, extra diodes have to be added to prevent the ‘short-circuit’ of neighbor switches. For the switch matrix inputs a ‘quasi’ capture mode can be configured via the data bit SMC (D3 ...
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... NXP Semiconductors The inverted bit stream of the ADC comparator generates the quasi-analog output voltage on pin INH, which can be used to control the analog voltage V An analog-to-digital conversion will have following steps: 1. Select an input channel via PxReq, see ADC-input is selected (see 2. The internal multiplexer switches over to the selected input; note that some time is needed to stabilize the loop, due to the RC network time constant ...
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... NXP Semiconductors up/down Fig 9. Table 25. Data byte D0 D1 [1] D2 [1] The UJA1023 expects to receive data byte D2 only if bit RxDL = 1 (bit 3 of byte D3 in the first I/O configuration data block, see Table 26. Byte D0 D1 [1] D2 [1] The UJA1023 expects to receive data byte D2 only if bit RxDL = 1 (bit 3 of byte D3 in the first I/O ...
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... NXP Semiconductors Table 27. Data byte Table 28. Byte D0 Bytes D1 and D2 if switch matrix is not configured (default Bytes D1 and D2 if switch matrix is configured D1 D2 Byte D3 D3 [1] Data bytes D2 and D3 are transmitted only if bit TxDL = 1 (bit 4 of byte D3 in the second I/O configuration data block, see ...
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... NXP Semiconductors 7.3 I/O block 7.3.1 I/O pins The I/O-pin structure of the UJA1023 is shown in Fig 10. I/O-pin structure The output is configurable as: • Push-pull • High-side switch • Low-side switch • High-impedance The input can be configured: • To capture on falling, rising or both edges • ...
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... NXP Semiconductors Table 29. Operation Power-on condition (high-impedance) High-impedance Low-side open-state Low-side close-state High-side open-state (Cyclic sense mode: off-state) High-side close-state (Cyclic sense mode: on-state) Push-pull HIGH-state Push-pull LOW-state Input with pull-up Input at threshold V (typically 3 V) Input at threshold V (typically 1.5 V) Capture edge at falling and ...
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... NXP Semiconductors Fig 11. INH structure 7.4 Configuration pins The structure of the configuration pins (Cx) is shown in a pull-up to the battery. The pull-up is switched on during node address configuration only. In all other cases the Cx have high-impedance behavior. In order to have a safety margin against ground shift the input threshold of the configuration pins is about 0.5 × ...
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... NXP Semiconductors Figure 13 termination. Fig 13. LIN transceiver states The first mode after power-on is the Off-line mode. The transmitter and receiver are both switched off, but wake-up events will be recognized. Any LIN wake-up event will wake-up the UJA1023. Within Sleep mode any wake-up event is automatically forwarded to the LIN (protocol) controller, the Normal mode will be entered and the LIN-transceiver automatically enters the Active mode ...
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... NXP Semiconductors • Entering Active mode out of Off-line mode results always in switching on the internal 30 kΩ pull-up resistor to battery 7.6 On-chip oscillator The on-chip oscillator is the time reference for all timers in the LIN controller, auto bit rate detector, ADC and LIN transceiver. ...
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... NXP Semiconductors 10. Static characteristics Table 32. Static characteristics [ 5 BAT VIO positive current flows into the IC; unless otherwise specified. Symbol Parameter Supply: pin BAT V supply voltage on pin BAT BAT I supply current on pin BAT BAT V V power fail detection BAT(pf) BAT voltage I/O reference (Px operating range): pin VIO ...
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... NXP Semiconductors Table 32. Static characteristics [ 5 BAT VIO positive current flows into the IC; unless otherwise specified. Symbol Parameter V LOW-level output voltage on OL(C3) pin C3 I short-circuit current on sc(C3) pin C3 I/O: pins HIGH-level input voltage V IH(th1) V LOW-level input voltage V IL(th1) V HIGH-level input voltage V IH(th2) ...
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... NXP Semiconductors [1] Valid for the UJA1023T/2R04/C; for the UJA1023T/2R04, V All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient [2] temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage ranges ...
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... NXP Semiconductors Table 33. Dynamic characteristics BAT VIO [1] unless otherwise specified. Symbol Parameter t symmetry of receiver P(RX)(sym) propagation delay rising edge with respect to falling edge LIN protocol controller t bus idle time-out to(idle) t bus dominant time-out to(dom) t bus recessive time-out to(rec) t network wake-up signal ...
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... NXP Semiconductors t bit V TXDL V BAT LIN BUS signal V RXDL1 receiving node 1 t p(rx1)f V RXDL2 receiving node 2 Fig 14. Timing diagram LIN transceiver UJA1023 Product data sheet t bit t t bus(dom)(max) bus(rec)(min bus(dom)(min) bus(rec)(max) t p(rx1)r t p(rx2)r All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 12. Application information Fig 15. Application Diagram 13. Test information Immunity against automotive transients (malfunction and damage) in accordance with LIN EMC Test Specification / Version 1.0; August 1, 2004. 13.1 Quality information This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive applications. ...
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... NXP Semiconductors 14. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... Document ID Release date UJA1023 v.5 20100817 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • V • Table 32 “Static – condition/value added for V – ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Short description of the UJA1023 . . . . . . . . . . . 5 7.1.1 LIN controller . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.2 LIN transceiver (including termination ...