TE28F800B3TA110 Intel, TE28F800B3TA110 Datasheet - Page 52

• Manufacturer Part Number: TE28F800B3TA110
• Manufacturer: Intel

Specifications of TE28F800B3TA110

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
10.0
10.1
10.1.1
52
Read (Array, Status, or Identifier)
Output Disable
Standby
Reset
Write
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].
2. X must be V
3. See DC Characteristics for V
4. Manufacturer and device codes can also be accessed in read identifier mode (A
5. Refer to
6. To program or erase the lockable blocks, hold WP# at V
7. RP# must be at GND
Table 25. Bus Operations
Table 28
Mode
IL
Operations Overview
Flash memory combines EEPROM functionality with in-circuit electrical program-and-erase
capability. The B3 flash memory device family utilizes a Command User Interface (CUI) and
automated algorithms to simplify Program and Erase operations. The CUI allows for 100%
CMOS-level control inputs and fixed power supplies during erasure and programming.
When V
Array, Read Status Register, Clear Status Register, and Read Identifier. The device provides
standard EEPROM read, standby, and Output-Disable operations. Manufacturer identification and
device identification data can be accessed through the CUI. All functions associated with altering
memory contents, namely program and erase, are accessible through the CUI. The internal Write
State Machine (WSM) completely automates Program and Erase operations, while the CUI signals
the start of an operation and the Status Register reports status. The CUI handles the WE# interface
to the data and address latches, as well as system status requests during WSM operation.
Bus Operations
The B3 flash memory device performs read, program, and erase in-system through the local CPU
or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller
bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#,
WE#, and RP#.
, V
Read
The flash memory has four read modes available: read array, read identifier, read status, and read
query. These modes are accessible independent of the V
command must be issued to the CUI to enter the corresponding mode. Upon initial device power-
up or after exit from reset, the device automatically defaults to read-array mode.
CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection
control; when active, it enables the flash memory device. OE# is the data output control, and it
drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at
V
IH
IH
for valid D
.
for control pins and addresses.
Figure 10
PP
0.2 V to meet the maximum deep power-down current specified.
< V
IN
PPLK
during a Write operation.
PPLK
illustrates a read cycle.
Table 25
, V
(1)
PP1
, the device will execute only the following commands successfully: Read
2, 5–7
Note
2–4
2, 7
, V
2
2
summarizes these bus operations.
PP2
, V
PP3
RP#
V
V
V
V
V
, V
IH
IH
IH
IH
IL
PP4
IH
.
voltages.
CE#
V
V
V
V
X
IH
IL
IL
IL
PP
OE#
V
V
V
X
X
IH
IH
IL
1
voltage. The appropriate Read Mode
–A
21
= 0). See
WE#
V
V
V
X
X
IH
IH
IL
Table
27.
High Z
High Z
High Z
DQ
D
D
OUT
IN
0–7
Datasheet
DQ
High Z
High Z
High Z
D
D
OUT
8–15
IN