TE28F800B3TA110 Intel, TE28F800B3TA110 Datasheet - Page 53

• Manufacturer Part Number: TE28F800B3TA110
• Manufacturer: Intel

Specifications of TE28F800B3TA110

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

10.1.2
10.1.3
10.1.4
10.1.5
Datasheet
Output Disable
With OE# at a logic-high level (V
high-impedance state.
Standby
Deselecting the device by bringing CE# to a logic-high level (V
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during Program or Erase operation, the device continues to consume active power until
the Program or Erase operation is complete.
Deep Power-Down / Reset
From read mode, RP# at V
impedance state, and turns off all internal circuits. After return from reset, a time t
until the initial read-access outputs are valid. A delay (t
reset before a write can be initiated. After this wake-up interval, normal operation is restored. The
CUI resets to read-array mode, and the Status Register is set to 80H.
Down/Reset Operations Waveforms” on page 50 (A)
If RP# is taken low for time t
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization can not occur because the
flash memory may be providing status information instead of array data. Intel
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
Write
A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard microprocessor write timings to control Flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
1. When RP# goes low, the device shuts down the operation in progress, a process that takes time
2. After this time t
3. In both cases, after returning from an aborted operation, the relevant time t
t
t
enter reset mode (if RP# is still logic low after t
Reset Operations Waveforms” on page 50
t
paragraph. However, in this case, these delays are referenced to the end of t
when RP# goes high.
PLRH
PLRH
PHEL
, see
must be waited before a Read or Write operation is initiated, as discussed in the previous
to complete.
Figure 14, “Deep Power-Down/Reset Operations Waveforms” on page 50
PLRH
, the part will either reset to read-array mode (if RP# has gone high during
IL
PLPH
for time t
IH
during a Program or Erase operation, the operation will be
), the device outputs are disabled. Output pins are placed in a
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
PLPH
deselects the memory, places output drivers in a high-
(C)).
PLRH
illustrates this case.
PHWL
, see
or t
Figure 14, “Deep Power-Down/
IH
PHEL
) places the device in standby
Figure 14, “Deep Power-
) is required after return from
®
PHQV
Flash memories
PLRH
PHQV
or t
rather than
is required
PHWL
(B)), or
/
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