MT48LC16M8A2TG-75 Micron Technology Inc, MT48LC16M8A2TG-75 Datasheet - Page 39

• Manufacturer Part Number: MT48LC16M8A2TG-75
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75

• Organization: 16Mx8
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Figure 30:
Figure 31:
WRITE with Auto Precharge
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Internal
States
Internal
States
READ With Auto Precharge Interrupted by a READ
READ With Auto Precharge Interrupted by a WRITE
Notes:
Notes:
COMMAND
COMMAND
ADDRESS
BANK m
ADDRESS
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
DQ
1. DQM is LOW.
1. DQM is HIGH at T2 to prevent D
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
1
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 32 on page 40).
Active
Page
READ - AP
BANK n,
Page Active
BANK n
COL a
T0
NOP
T0
READ with Burst of 4
READ - AP
BANK n,
Page Active
Page Active
BANK n
COL a
T1
T1
NOP
CL = 3 (BANK n)
READ with Burst of 4
CL = 3 (BANK n)
T2
T2
NOP
NOP
39
BANK m,
READ - AP
T3
BANK m
T3
COL d
OUT
D
NOP
OUT
a
Interrupt Burst, Precharge
READ with Burst of 4
a + 1 from contending with D
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR is met, where
TRANSITIONING DATA
BANK m,
WRITE - AP
TRANSITIONING DATA
COL d
BANK m
T4
T4
CL = 3 (BANK m)
D
NOP
d
IN
Interrupt Burst, Precharge
D
WRITE with Burst of 4
OUT
a
t
RP - BANK n
T5
T5
d + 1
NOP
NOP
D
IN
D
a + 1
128Mb: x4, x8, x16 SDRAM
OUT
t
RP - BANK n
t
WR begins when the READ to
T6
T6
d + 2
NOP
NOP
D
IN
D
OUT
©1999 Micron Technology, Inc. All rights reserved.
d
IN
DON’T CARE
DON’T CARE
at T4.
Idle
T7
T7
t WR - BANK m
d + 3
NOP
NOP
D
t RP - BANK m
IN
Precharge
Write-Bac k
D
d + 1
OUT
Idle
Operations