MT48LC16M8A2TG-75 Micron Technology Inc, MT48LC16M8A2TG-75 Datasheet - Page 61

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MT48LC16M8A2TG-75

Manufacturer Part Number
MT48LC16M8A2TG-75
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC16M8A2TG-75

Organization
16Mx8
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant

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Figure 45:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMU
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CKE
CLK
A10
DQ
t CKS
t CMS
t AS
t AS
t AS
Single READ – With
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
3. READ command not allowed or
NOP
x8: A11 = “Don’t Care.”
t CL
Auto Precharge
T2
NOP 2
t CH
T3
NOP 2
ENABLE AUTO PRECHARGE
t CMS
61
COLUMN m 3
BANK
T4
READ
t
t CMH
CAS Latency
RAS would be violated.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t AC
t RP
D
T6
128Mb: x4, x8, x16 SDRAM
OUT
NOP
t OH
m
t HZ
©1999 Micron Technology, Inc. All rights reserved.
ACTIVE
ROW
BANK
T7
ROW
Timing Diagrams
T8
NOP
DON’T CARE
UNDEFINED

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