MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 212

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

transfer. Edge-triggered latch B is clocked by the rising edge of BCLK and latches the
data from latch A for use by internal logic.
Figure 7-48 illustrates the data read timing for both normal operation and DLE mode.
During normal operation (i.e., DLE mode disabled), latch A is always transparent, and by
the rising edge of BCLK, read data is latched. Data must meet setup and hold time
specifications #15 and #16 in this case. When the DLE mode is enabled, the data can be
latched by the rising edge of BCLK or the falling edge of DLE, depending on the timing for
DLE.
7-70
TA, TEA, TBI
EXTERNAL
DATA BUS
DLE
Figure 7-47. DLE Mode Block Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER’S MANUAL
TRANSPARENT
Go to: www.freescale.com
LATCH - A
D
G
Q
EDGE-TRIGGERED
LATCH - B
D
BCLK
Q
WRITE DATA
TERMINATION
CONTROL
LATCHED
READ DATA
MOTOROLA