MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 437

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Cache, 1-4, 2-8
Cache Coherency, 4-10
Cache Controller, 3-2, 3-28, 4-4, 4-8, 4-12
Cache Inhibited, see Caching Modes
Cache Line, 4-3
Caching Modes, 4-6
Caching Operation, 4-3
Calculate Stage, see Integer Unit Pipeline
CM Field, 4-6, 5-8, see also Descriptors
Conditional Branch, 7-50
Conditional Tests, 9-15, 9-17
Control Signals, 7-1, 7-9
Copyback, see Caching Modes
Data Bus, 7-1, 7-3
Data Format, 1-9, 9-7
INDEX-2
Burst Mode Operations, 4-11
Data, 2-3, 2-8, 3-1, 3-12, 7-44, 8-7, 8-18
Exceptions, 8-7, 8-18
Instruction Prefetches, 4-13
Instruction, 3-1, 8-7, 8-18
Misaligned Accesses, 4-11
Page Descriptors, 4-5
Replacement Algorithm, 4-4
Retry Operation, 4-12
Shared Data, 4-9, 4-10
D-Bit, 4-6
Dirty, 4-3
Format, 4-2
Invalid, 4-3; Timing, 10-8
V-Bit, 4-3
Valid, 4-3
Cache Inhibited, 4-7
Copyback, 4-6, 7-60
Default, 4-6
Nonserialized, 4-6
Serialized, 4-6
Write-Through, 4-6
Floating-Point IEEE Tests, 9-17, 9-18, 9-25
Unordered Conditions, 9-17, 9-18
Extended Precision, 9-12, 9-21, 9-23, 9-24
Floating-Point Conversion of, 9-12
Packed Decimal Real, 9-22
–C–
–D–
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER’S MANUAL
Go to: www.freescale.com
Data Latch Enable (DLE) Mode, 1-2, 5-5, 5-14,
Data Registers, 2-4
Data Types, 9-7
Decode Stage, see Integer Unit Pipeline
Demand Memory, 3-1
Denormalized Numbers, see Data Types
Descriptors, 3-8, 3-12
Direct Memory Access (DMA), 7-56
Dirty Data, 4-1, 5-8
Disabling JTAG, 6-13
Disregard Request Condition, 7-55
Double Bus Fault, 7-43, 8-8, 8-18
DRVCTL.T, 6-3, 6-12
Dynamic Bus Sizing, 7-3
Effective Address (<ea>), 2-3
Execute Stage, see Integer Unit Pipeline
Exception Handler, 8-4
Exception Processing, 1-6, 2-5, 7-36, 7-37, 7-43,
Exception Vector, 2-7
Exceptions
7-70, A-5
Denormalized Numbers, 1-9, 9-12, 9-22,
Infinities, 1-9
NANs, 1-9, 9-17
Normalized Numbers, 1-9, 9-16, 9-33
Unnormalized Numbers, 9-12, 9-22, 9-23
Zeros, 1-9
CM Field, 4-6, 5-8
Field Definitions, 3-13
Indirect, 3-9, 3-14; PDT Field, 3-17
Invalid, 3-9, 3-14
M-Bit, 3-21
Page, 3-12, 3-13, 3-17, 3-23, 3-24, 4-5
Resident, 3-14
S-Bits, 3-23
Table, 3-12, 3-13, 3-24; UDT Field, 3-19
U-Bit, 3-21
W-Bits, 3-24
A-6
Table, 8-1, 8-4
Access Error, 1-5, 3-23, 3-24, 5-14, 7-37,
Access Fault, 3-9, 8-6, 8-7
Address Error, 7-6, 7-43, 8-8
9-23, 9-16
7-43, 9-21, A-6
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