71V3558S133PF

Manufacturer Part Number71V3558S133PF
ManufacturerIDT, Integrated Device Technology Inc
71V3558S133PF datasheet
 


Specifications of 71V3558S133PF

Density4.5MbAccess Time (max)4.2ns
Sync/asyncSynchronousArchitectureSDR
Clock Freq (max)133MHzOperating Supply Voltage (typ)3.3V
Address Bus18bPackage TypeTQFP
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current300mAOperating Supply Voltage (min)3.135V
Operating Supply Voltage (max)3.465VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count100
Word Size18bNumber Of Words256K
Lead Free Status / Rohs StatusNot Compliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Page 10/26

Download datasheet (478Kb)Embed
PrevNext
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
First Address
Second Address
Third Address
(1)
Fourth Address
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
First Address
Second Address
Third Address
(1)
Fourth Address
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CYCLE
n+29
CLOCK
(2)
ADDRESS
A29
(A0 - A16)
(2)
CONTROL
C29
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
I/O [0:31], I/O P[1:4]
NOTES:
1. This assumes CEN, CE
, CE
, CE
are all true.
1
2
2
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
LBO
Sequence 1
Sequence 2
A1
A0
A1
A0
0
0
0
0
1
0
1
0
1
1
1
1
LBO
Sequence 1
Sequence 2
A1
A0
A1
A0
0
0
0
0
1
1
1
0
1
1
1
0
n+30
n+31
n+32
n+33
A30
A31
A32
A33
C30
C31
C32
C33
D/Q28
D/Q29
D/Q30
D/Q31
6.42
10
Commercial and Industrial Temperature Ranges
Sequence 3
Sequence 4
A1
A0
A1
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
Sequence 3
Sequence 4
A1
A0
A1
1
1
0
1
0
1
1
0
1
0
0
0
0
0
1
1
n+34
n+35
n+36
A34
A35
A36
C34
C35
C36
D/Q32
D/Q33
D/Q34
5281 drw 03
A0
1
0
1
0
5281 tbl 10
A0
1
0
1
0
5281 tbl 11
n+37
A37
C37
D/Q35
,