71V3558S133PF

Manufacturer Part Number71V3558S133PF
ManufacturerIDT, Integrated Device Technology Inc
71V3558S133PF datasheet
 


Specifications of 71V3558S133PF

Density4.5MbAccess Time (max)4.2ns
Sync/asyncSynchronousArchitectureSDR
Clock Freq (max)133MHzOperating Supply Voltage (typ)3.3V
Address Bus18bPackage TypeTQFP
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current300mAOperating Supply Voltage (min)3.135V
Operating Supply Voltage (max)3.465VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count100
Word Size18bNumber Of Words256K
Lead Free Status / Rohs StatusNot Compliant  
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IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
CEN
(5)
R/W
Chip
ADV/LD
Enable
L
L
Select
L
L
H
Select
L
L
X
X
H
L
X
X
H
L
X
Deselect
L
L
X
X
H
H
X
X
X
NOTES:
1. L = V
, H = V
, X = Don’t Care.
IL
IH
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
, or CE
3. Deselect cycle is initiated when either (CE
1
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE
= L, CE
= L, CE
1
2
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
OPERATION
READ
WRITE ALL BYTES
(2)
WRITE BYTE 1 (I/O[0:7], I/O
)
P1
(2)
WRITE BYTE 2 (I/O[8:15], I/O
)
P2
(2,3)
WRITE BYTE 3 (I/O[16:23], I/O
)
P3
(2,3)
WRITE BYTE 4 (I/O[24:31], I/O
)
P4
NO WRITE
NOTES:
1. L = V
, H = V
, X = Don’t Care.
IL
IH
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
BWx
ADDRESS
PREVIOUS CYCLE
USED
Valid
External
X
X
External
X
Valid
Internal
LOAD WRITE /
BURST WRITE
X
Internal
LOAD READ /
BURST READ
X
X
X
X
X
DESELECT / NOOP
X
X
X
is sampled high or CE
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
2
2
= H on these chip enables. Chip is deselected if any one of the chip enables is false.
2
R/W
H
L
L
L
L
L
L
6.42
9
Commercial and Industrial Temperature Ranges
CURRENT CYCLE
(2 cycles later)
LOAD WRITE
LOAD READ
BURST WRITE
(2)
(Advance burst counter)
BURST READ
(2)
(Advance burst counter)
(3)
DESELECT or STOP
NOOP
(4)
SUSPEND
Previous Value
BW
BW
BW
(3)
1
2
3
X
X
X
L
L
L
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
I/O
(7)
D
(7)
Q
(7)
D
(7)
Q
HiZ
HiZ
5281 tbl 08
BW
(3)
4
X
L
H
H
H
L
H
5281 tbl 09