71V3558S133PF

Manufacturer Part Number71V3558S133PF
ManufacturerIDT, Integrated Device Technology Inc
71V3558S133PF datasheet
 


Specifications of 71V3558S133PF

Density4.5MbAccess Time (max)4.2ns
Sync/asyncSynchronousArchitectureSDR
Clock Freq (max)133MHzOperating Supply Voltage (typ)3.3V
Address Bus18bPackage TypeTQFP
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current300mAOperating Supply Voltage (min)3.135V
Operating Supply Voltage (max)3.465VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count100
Word Size18bNumber Of Words256K
Lead Free Status / Rohs StatusNot Compliant  
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IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Symbol
Parameter
|I
|
Input Leakage Current
LI
(1)
LBO Input Leakage Current
|I
|
LI
|I
|
Output Leakage Current
LO
V
Output Low Voltage
OL
V
Output High Voltage
OH
NOTE:
1. The LBO pin will be internally pulled to V
if it is not actively driven in the application.
DD
Symbol
Parameter
I
Device Selected, Outputs Open,
DD
Operating Power
ADV/LD = X, V
Supply Current
V
> V
IN
IH
I
Device Deselected, Outputs Open,
SB1
CMOS Standby
V
= Max., V
DD
Power Supply Current
(2,3)
= 0
I
Device Deselected, Outputs Open,
SB2
Clock Running Power
V
= Max., V
DD
Supply Current
(2.3)
= f
MAX
I
Device Selected, Outputs Open,
SB3
Idle Power
CEN > V
Supply Current
V
> V
IN
HD
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
inputs are cycling at the maximum frequency of read cycles of 1/t
MAX,
3. For I/Os V
= V
– 0.2V, V
= 0.2V. For other inputs V
HD
DDQ
LD
I/O
6
5
4
3
tCD
(Typical, ns)
2
1
20 30 50
80
100
Capacitance (pF)
Figure 2. Lumped Capacitive Load, Typical Derating
Test Conditions
V
= Max., V
= 0V to V
DD
IN
V
= Max., V
= 0V to V
DD
IN
V
= 0V to V
, Device Deselected
OUT
DDQ
I
= +8mA, V
= Min.
OL
DD
I
= -8mA, V
= Min.
OH
DD
200MHz
Test Conditions
Com'l Only
Com'l
400
= Max.,
DD
(2)
or < V
, f = f
IL
MAX
40
> V
or < V
, f
IN
HD
LD
130
> V
or < V
, f
IN
HD
LD
40
, V
= Max.,
IH
DD
(2,3)
or < V
, f = f
LD
MAX
; f=0 means no input lines are changing.
CYC
= V
– 0.2V, V
= 0.2V.
HD
DD
LD
V
/2
DDQ
50
Input Pulse Levels
Z
= 50
,
0
Input Rise/Fall Times
5281 drw 04
Input Timing Reference Levels
Figure 1. AC Test Load
Output Timing Reference Levels
AC Test Load
,
200
5281 drw 05
6.42
15
Commercial and Industrial Temperature Ranges
Min.
Max.
___
DD
___
DD
___
___
0.4
2.4
166MHz
133MHz
100MHz
Ind
Com'l
Ind
Com'l
350
360
300
310
250
40
45
40
45
40
120
130
110
120
100
40
45
40
45
40
0 to 3V
See Figure 1
Unit
5
µ A
30
µA
5
µ A
V
___
V
5281 tbl 21
Ind
Unit
255
mA
45
mA
110
mA
45
mA
5281 tbl 22
2ns
1.5V
1.5V
5281 tbl 23