NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 2

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

PIN DESCRIPTION
Pin N5
10
11
12
13
14
15
16
17
18
19
20
22
23
24
1
2
3
4
5
6
7
8
9
GND/PGND
Skip/AGND
Pin Name
BO adj.
PG adj.
PG out
V
CS/FF
Bridge
OVP2
on/off
V
DRV
LBO
Fold
Vref
V
CTRL
MU
SS
V
CS
ML
FB
Rt
boot
CC
M
The open−collector power good signal
PFC line input voltage sensing
PFC current amplifier output
PFC Error amplifier output
The power good trip level
Brown−out adjustment
The LLC feedback pin
The 5 V reference pin
Lower−side MOSFET
Upper−side MOSFET
The controller supply
GND (B)/PGND (A)
PFC current sense
Skip (B)/AGND (A)
Bootstrapped Vcc
Redundant OVP
PFC drive signal
Remote control
Fast−fault input
PFC feedback
PFC fold back
Half−bridge
Function
Soft−start
ON/OFF
Figure 1. Pin Connections
BO adj.
PG adj.
VCTRL
PG out
OVP2
LBO
Vref
VM
SS
FB
http://onsemi.com
Rt
1
2
24
A capacitor to ground sets the LLC soft−start duration
A resistive arrangement sets the maximum and minimum
switching frequencies with opto coupler−based feedback
capabilities.
This pin is low when V
below a level adjusted by PGadj pin.
When pulled low, the circuit operates: the PFC starts first and
once FB is in regulation, the LLC is authorized to work. When
left open, the controller is in idle mode.
This pin sets the on and off levels for the PFC powering the
LLC converter
This pin delivers a stable voltage for threshold adjustments
From the Vref pin, a dc level sets the trip point for the PFC
bulk voltage at which the PG out signal is down.
A fully latched OVP monitoring the PFC bulk independently
from FB pin.
Monitors the boost bulk voltage and regulates it. It also serves
as a quick auto−recovery OVP
PFC error amplifier compensation pin
A resistor to ground sets the maximum power level
Line feed forward and PFC brown−out
This pin selects the power level at which the frequency starts
to reduce gradually.
This pin senses the inductor current and also programs the
maximum sense voltage excursion
When pulled above 1 V, the LLC stops and re−starts via a full
soft−start sequence.
This pin is either used as the analog GND for the signal circuit
(A) or for skip operation (B).
The controller ground for the driving loop (A) or the lump
ground pin for all circuits (B)
The driving signal to the PFC power MOSFET
The power supply pin for the controller, 20 V max.
Drive signal for the lower side half−bridge MOSFET
This pin connects to the LLC half−bridge
Drive signal for the upper side half−bridge MOSFET
The bootstrapped V
Vboot
MU
Bridge
ML
V
DRV
GND/PGND
Skip/AGND
CS/FF
CS
Fold
CC
CC
bulk
Pin Description
for the floating driver
is ok, opens when V
bulk
passes