NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 26

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

PFC Frequency Foldback
section to improve the efficiency at light load. Thanks to
V
to the (V
Where:
in
NCP1910 implements frequency foldback feature on PFC
♦
♦
♦
♦
2
feed−forward feature, the output power is proportional
oscillator and hence control the nominal operating
frequency.
frequency foldback starts.
operating frequency according to the error
information between V
V
I
I
V
I
Ct(min)
Ct
Ct(fold)
CTRL(min)
fold
CTRL
and I
determines the power level at which the
limits the minimum operating frequency.
steals the I
Ct(min)
− V
).
CTRL(min)
provide the charging current for
F
Ct
sw(fold)
and hence reduces the
). The PFC frequency foldback
Vfold
Vref
fold
Vctrl
Figure 51. The Relationship between Frequency and V
Vfold(max)
and (V
Figure 50. The PFC Frequency Foldback Block
V
Vctrl(min)
CTRL
fold
– 0.4
−
Ict(fold)
http://onsemi.com
Q
Q
R
S
V
26
fold
is hence done by comparing (V
V
feature is depicted in Figure 50.
the PFCok signal in Figure 50 is asserted high.
foldback starts by adjust the resistor divider between V
pin and fold pin. Also, the frequency foldback can be
disabled by grounding fold pin.
is depicted in Figure 51.
Ict
fold
The simplified block diagram of PFC frequency foldback
The frequency foldback is disabled at startup, i.e. before
The user can adjust the power level at which the frequency
The relationship between operating frequency and V
♦
♦
Vdd
PFC OK
The slope is fixed internally.
The power level at which fre-
quency starts reducing is ad-
justable by modifying V
, the voltage on Fold pin.
is fixed inside.
frequency foldback, which is around 2 V typically.
The transient slope of frequency foldback vs. V
V
F
fold(max)
sw
V
CTRL
Grand Reset
PFC BO
Ict(min)
Oscillator section
−V
is to limit the maximum power level of
CTRL(min)
PFCOSC
CTRL
“0” / ”1”
V
PREF
T Power
fold
/ 10%V
CTRL
.
PREF
− V
CTRL(min)
) with
CTRL
CTRL
REF