NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 30

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

PFC Abnormal
When V
– 0.1 V, for more than t
t
operating without correct operation of PFC stage.
LLC Section
Current Controlled Oscillator (CCO)
circuitry allowing operation from 50 kHz up to 1 MHz.
which is proportional to the current flowing out from the
R
on this capacitor reaches V
disabled during discharge period so the dead time length is
given by the discharge current sink capability. Discharge
sink is disabled when voltage on the timing capacitor
reaches zero and charging cycle starts again. C
to disable the oscillator when either of “turn−off LLC”
signals arrives.
DEL2
t
The PFC abnormal is detected by sensing V
The main purpose of this feature is to avoid LLC from
The current controlled oscillator features a high−speed
The internal timing capacitor C
pin. The discharging current i
Feedback
opto-coupler
, LLC shuts down. It is latches off protection.
CTRL
R
max
stays at V
R
C
Figure 57. The Current Controlled Oscillator Architecture and Configuration
SS
SS
PFCabnormal
CTRL(max)
R
R
Ctmax
min
SS
V
t
SS_RST
DT
, or lower than V
, PFC turns off first. After
. The output drivers are
Grand Reset
t
is applied when voltage
is charged by current
-
+
V
Rt
t
is grounded
CTRL
C
CTRL(min)
t
http://onsemi.com
level.
VDD
Grand Reset
CS/FF > V
Q
Q
S
R
I
DT
30
CS1
However, as a D−flip−flop that creates division−by−two
internally provides two outputs (A and B in Figure 57), the
final effective signal on LLC driver outputs (ML and MU)
switches between 25 kHz and 500 kHz. The CCO is
configured in such a way that if the current that flows out
from the R
up.
minimum operating frequency with high accuracy. The
designer also needs to limit maximum operating and startup
frequency. All these parameters can be adjusted by using
external components connected to the R
Figure 57.
minimum, maximum and startup frequency respectively:
For the resonant applications, it is necessary to adjust
The following approximate relationships hold for the
R
S
Q
Q
t
LLC_PG
pin increases, the switching frequency also goes
V
+
-
Ctmax
Disable LLC ML and MU
t
Grand Reset
DEL2
LLC_BO
elapsed
D
Clk
R
S
Q
Q
t
B
A
pin as shown in
Grand Reset
LLCenable
Latch
for ML
for MU