NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 23

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

and a 980 mV voltage source, V
the LBO pin to maintain the pin level near 1 V. Then a 50 ms
blanking delay, t
fault is detected. The main goal of the 50 ms lag is to help
meet the hold−up requirements. In case of a short mains
interruption, no fault is detected and hence, both PFC and
LLC keep operating. In addition, LBO pin being kept at
980 mV, there is almost no extra delay between the line
recovery and the occurrence of a proper voltage applied to
LBO pin, that otherwise would exist because of the large
capacitor typically placed between LBO pin and ground to
filter the input voltage ripple. As a result, the NCP1910
effectively “blanks” any mains interruption that is shorter
than 25 ms (minimum guaranteed value of the 50 ms timer).
timer is activated that sets a 50 ms window during which a
fault can be detected. This is the role of the t
Figure 46:
•
•
When the PFC_BO signal is high:
•
•
•
voltage remains below when: V
is released open or UVP or Thermal Shutdown. This is to
guarantee that the circuit starts operation in the right state,
which is “PFC_BO” high. When the NCP1910 is ready to
work, the pnp transistor turns off and the circuit enables the
I
but at startup, I
Line Brown−Out Network Calculation
after bridge diode, the monitored voltage can be very
different depending on the phase:
•
LBOH
Conversely, if V
At the end of this blanking delay (t
At startup, a pnp transistor ensures that the LBO pin
Also, I
If the line brown−out network is connected to the voltage
If V
(t
and PFC_BO signal is asserted high.
If V
t
The PFC driver is disabled, and the V
grounded to recover operation with a soft−start when
the fault has gone.
The V
pin.
The I
that lowers the LBO pin voltage for hysteresis purpose.
Before operation, the PFC stage is off and the input
bridge acts as a peak detector. As a consequence, the
input voltage is approximately flat and nearly equates
the ac line amplitude: <V
is the rms voltage of the line. As depicted in previous
section, the I
purpose of adjustable line brown−out hysteresis; hence,
the average voltage applied to LBO pin is:
LBO(window)
LBO(window)
.
LBOcomp
LBOcomp
LBOH
LBO(clamp)
LBOH
current source (7 mA typically) is enabled
LBOH
, no fault is detected.
is enabled whenever the part is in off mode,
LBOH
is high during the second 50 ms delay
remains low for the duration of the
), a line brown−out condition is confirmed
LBO(blank)
LBO
voltage source is removed from LBO
is disabled until V
turns on before PFC operates for the
goes below 1 V, V
, is activated during which no
in
> = √2 V
CC
LBO(clamp)
< UVLO or ON/OFF pin
ac,rms
LBO(blank)
CC
LBOcomp
CTRL
reaches V
, is connected to
, where V
LBO(window)
pin is
), another
turns high
http://onsemi.com
CC(on)
ac,rms
in
.
23
•
Where:
account the LBO pin voltage ripple (first approximation).
Re−arranging the Equation 9 and 10, the network connected
to LBO pin can be calculated with the following equations:
Where:
R
The term
If as a rule of the thumb, we will assume that
After the PFC stage has started operation, the input
voltage becomes a rectified sinusoid and the average
voltage becomes <V
decays 2/π of the peak value of rms input voltage.
Hence, the average voltage applied to LBO pin is:
<V
And because of the ripple on the LBO pin, the
minimum value of V
♦
♦
♦
♦
LBOL
V
V
If R
V
LBO
LBO
LBO
between LBO pin and ground.
between V
LBO
f
f
R
R
LBO
line
R
f
LBOL
LBOU
LBOL
LBOU
LBO
^
+
+ 2 V
] 2 V
+
> = (2/p) √2 V
is the line frequency.
is the sensing network pole frequency.
+
@
2
p
1 *
1 *
0.967
is low side resistor of the dividing resistors
is upper side resistor of the dividing resistors
+
<< R
R
R
1
2 V
2pR
LBOU
in
1
LBOU
ac,rms
ac,rms
3f
f
3f
f
1 *
R
LBO
LBO
and LBO pin.
I
line
LBOU
@
LBOH
ac,rms
LBOU
line
LBOU
p
2
) R
@ R
@
3f
R
R
f
@
of Equation 10 enables to take into
in
LBO
LBO
p
2
R
LBOU
LBOU
line
ac,rms
R
,
V
V
> = (2/p) √2 V
) R
R
2 @ V
LBOL
@
LBOL
LBOL
LBOL
ac,on
ac,off
LBOU
V
V
R
R
is around:
ac,on
ac,off
LBOL
LBOL
LBOL
) R
) R
R
ac,on
R
C
) V
* 1 @
LBOL
LBOL
) R
LBO
* 1 @
LBOL
LBOL
LBOT
LBOL
/(R
* I
* I
V
ac,rms
I
LBOH
* 1 R
LBOU
LBOT
V
I
LBOH
LBOH
LBOH
LBOT
, which
+ R
f
R
LBO
LBOL
LBOL
LBOL
(eq. 10)
(eq. 12)
(eq. 11)
+
(eq. 9)
f
10
).
line
.