NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 28

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

PFCok Signal
The PFC provides a “PFCok” signal to:
•
•
•
•
normal operation, i.e. its output is above 95% of normal
output, and low otherwise.
This “PFCok” signal is high when the PFC stage is in
maximum sink and source of output current capability
of OTA is around 30 mA. Due to the “V
block (VLD), when the V
extra 200 mA current source (I
raise V
from dropping too low and improve the transient
enable the dynamic response enhancer (I
below 95%, finish of the PFC soft−start,
enable the PFC frequency foldback,
enable the timer (t
converter,
enable the timer (t
converter once “PFCok” is asserted low or V
lower than PG level after LLC−HB has started.
CTRL
rapidly. Hence prevent the PFC output
FB
DEL1
DEL2
95% V
V
), which is to start the LLC−HB
), which is to stop LLC−HB
PREF
PREF
230 mA raises V
when V
V
PREF
FB
−100
−150
−200
−250
Figure 53. V
is below 95% V
−50
VLD
+
+
50
−
−
0
FB
in Figure 52) will
DRV
is below 95%
2
PFC
VLD
Figure 54. PFCok Signal Block Diagram
out
REG
VLD
FB
CTRL
Low Detect”
vs. Current Flowing in/out From V
PREF
) if V
bulk
2.2
rapidly
, an
is
http://onsemi.com
bulk
is
Grand Reset
2.4
28
PFC_BO
Latch
decoupling capacitor next to feedback pin to prevent from
noise impact.
V
Refer to Figure 54. “PFCok” signal is low when
•
•
•
“PFCok” signal is high when
•
•
FB
It is recommended to add a typical 100 pF capacitor C
No DRV when V
above 105% V
response performance. The relationship between
current flowing in/out V
in Figure 53.
the PFC stage start−up, or
any latch off signal arrives, or
line brown−out activates.
DRV starts operating and the PFC stage is above 95%
of target, i.e. the VLD comparator output is high, or
the PFC stage is above 100% target, i.e. PFC
comparator output is high.
2.6
CTRL
PREF
2.8
FB
R
S
is
Pin
Q
Q
CTRL
3
pin and V
PFC_OK
FB
is as shown
REG
FB