DS3172+ Maxim Integrated Products, DS3172+ Datasheet - Page 157

• Manufacturer Part Number: DS3172+
• Description: IC TXRX DS3/E3 DUAL 400-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3172+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 2
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 328mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

12.6 HDLC
12.6.1 HDLC Transmit Side Register Map
The transmit side utilizes five registers.
Table 12-17. Transmit Side HDLC Register Map
12.6.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 12 to 8: Transmit HDLC Data Storage Available Level (TDAL[4:0]) – These five bits indicate the minimum
number of bytes ([TDAL x 8}+1) that must be available for storage (do not contain data) in the Transmit FIFO for
HDLC data storage to be available. For example, a value of 21 (15h) results in HDLC data storage being available
(THDA=1) when the Transmit FIFO has 169 (A9h) bytes or more available for storage, and HDLC data storage not
being available (THDA=0) when the Transmit FIFO has 168 (A8h) bytes or less available for storage.
Default value (after reset) is 128 bytes minimum available.
Bit 6: Transmit Packet Start Disable (TPSD) – When 0, the Transmit Packet Processor will continue sending
packets after the current packet end. When 1, the Transmit Packet Processor will stop sending packets after the
current packet end.
Bit 5: Transmit FCS Error Insertion (TFEI) – When 0, the calculated FCS (inverted CRC-16) is appended to the
packet. When 1, the inverse of the calculated FCS (non-inverted CRC-16) is appended to the packet causing an
FCS error. This bit is ignored if transmit FCS processing is disabled (TFPD = 1).
Bit 4: Transmit Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag sequence (7Eh).
When 1, inter-frame fill is done with all ‘1’s.
(0,2,4,6)AAh
(0,2,4,6)ACh
(0,2,4,6)AEh
(0,2,4,6)A0h HDLC.TCR
(0,2,4,6)A2h HDLC.TFDR
(0,2,4,6)A4h HDLC.TSR
(0,2,4,6)A6h HDLC.TSRL
(0,2,4,6)A8h HDLC.TSRIE
Address
15
--
--
0
7
0
Register
TPSD
14
--
--
--
--
0
6
0
HDLC.TCR
HDLC Transmit Control Register
(0,2,4,6)A0h
HDLC Transmit Control Register
HDLC Transmit FIFO Data Register
HDLC Transmit Status Register
HDLC Transmit Status Register Latched
HDLC Transmit Status Register Interrupt Enable
Unused
Unused
Unused
Register Description
TFEI
13
--
0
5
0
TDAL4
TIFV
12
0
0
4
157
TDAL3
TBRE
11
1
3
0
TDAL2
TDIE
10
0
2
0
TDAL1
TFPD
9
0
1
0
TFRST
TDAL0
8
0
0
0