SC26C92C1A,518 NXP Semiconductors, SC26C92C1A,518 Datasheet - Page 21

• Manufacturer Part Number: SC26C92C1A,518
• Description: IC DUART SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC26C92C1A,518

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: Transceiver
• Fifo's: 8 Byte
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 0.2304 MBd
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 10 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5047-2; 935051510518; SC26C92C1A,518; SC26C92C1A-T; SC26C92C1A-T

Philips Semiconductors
SOPR – Set the Output Port Bits (OPR)
SOPR[7:0] – Ones in the byte written to this register will cause the
corresponding bit positions in the OPR to set to 1. Zeros have no
effect.
ROPR – Reset Output Port Bits (OPR)
ROPR[7:0] – Ones in the byte written to the ROPR will cause the
corresponding bit positions in the OPR to set to 0. Zeros have no effect.
Table 6. Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
Asynchronous UART communications can tolerate frequency error
of 4.1% to 6.7% in a “clean” communications channel. The percent
of error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a
stop bit length of 9/16 is used, the error tolerance will approach 0
due to a variable error of up to 1/16 bit time in receiver clock phase
alignment to the start bit.
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG (see Table 5).
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 6.
2000 Jan 31
NOTE: Duty cycle of 16X clock is 50%
Dual universal asynchronous receiver/transmitter (DUART)
NORMAL RATE
1050
1200
1800
2000
2400
4800
7200
9600
134.5
150
200
300
600
230.4K
110
115.2K
50
75
14.4K
19.2K
28.8K
38.4K
57.6K
(BAUD)
ACTUAL 16X
CLOCK (kHz)
115.2
153.6
230.4
307.2
460.8
614.4
921.6
1843.2K
3686.4K
16.756
19.2
28.8
32.056
38.4
76.8
0.8
1.2
1.759
2.153
2.4
3.2
4.8
9.6
1%.
ERROR (%)
-0.069
-0.260
0.059
0.175
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
Table 7. ACR 6:4 Field Definition
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 7.
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR[7], which results in
the generation of an interrupt output if IMR[7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
IPCR – Input Port Change Register
IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
IPCR[3:0] – IP3, IP2, IP1, IP0 Change-of-State
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
ISR – Interrupt Status Register
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the Interrupt Mask
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit
in the IMR is also a ‘1’, the INTRN output will be asserted (Low). If
the corresponding bit in the IMR is a zero, the state of the bit in the
ISR has no effect on the INTRN output. Note that the IMR does not
mask the reading of the ISR – the true status will be provided
regardless of the contents of the IMR. The contents of this register
are initialized to H‘00’ when the DUART is reset.
NOTE: The timer mode generates a squarewave.
000
001
010
011
100
101
110
111
ACR
6:4
Counter
Counter
Counter
Counter
Timer (square wave)
Timer (square wave)
Timer (square wave)
Timer (square wave)
MODE
External (IP2)
TxCA – 1X clock of Channel A
transmitter
TxCB – 1X clock of Channel B
transmitter
Crystal or external clock
(X1/CLK) divided by 16
External (IP2)
External (IP2) divided by 16
Crystal or external clock
(X1/CLK)
Crystal or external clock
(X1/CLK) divided by 16
CLOCK SOURCE
Product specification
SC26C92