AT89C5115 Atmel Corporation, AT89C5115 Datasheet - Page 8

• Manufacturer Part Number: AT89C5115
• Manufacturer: Atmel Corporation

Specifications of AT89C5115

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 20
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 0.5
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Read-Modify-Write
Instructions
Quasi Bi-directional Port
Operation
8
AT89C5115
Some instructions read the latch data rather than the pin data. The latch based instruc-
tions read the data, modify the data and then rewrite the latch. These are called ’Read-
Modify-Write’ instructions. Below is a complete list of these special instructions (See
Table 1). When the destination operand is a Port or a Port bit, these instructions read
the latch rather than the pin:
Table 1. Read/Modify/Write Instructions
It is not obvious that the last three instructions in this list are Read-Modify-Write instruc-
tions. These instructions read the port (all 8 bits), modify the specifically addressed bit
and write the new byte back to the latch. These Read-Modify-Write instructions are
directed to the latch rather than the pin in order to avoid possible misinterpretation of
voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the
base of an external bipolar transistor cannot rise above the transistor’s base-emitter
junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by
the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch
rather than the pins returns the correct logic one value.
Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as ’quasi-bidi-
rectional’ Ports. When configured as an input, the pin impedance appears as logic one
and sources current in response to an external logic zero condition. Resets write logic
one to all Port latches. If logical zero is subsequently written to a Port latch, it can be
returned to input conditions by a logic one written to the latch.
Note:
Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1)
to aid this logic transition See Figure 2. This increases switch speed. This extra pull-up
sources 100 times normal internal circuit current during 2 oscillator clock periods. The
internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist
of three p-channel FET (pFET) devices. A pFET is on when the gate senses logic zero
and off when the gate senses logic one. pFET #1 is turned on for two oscillator periods
immediately after a zero-to-one transition in the Port latch. A logic one at the Port pin
turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form
a latch to drive logic one. pFET #2 is a very weak pull-up switched on whenever the
MOV Px.y, C
Instruction
CLR Px.y
SET Px.y
DJNZ
DEC
ANL
ORL
XRL
CPL
JBC
INC
Port latch values change near the end of Read-Modify-Write insruction cycles. Output
buffers (and therefore the pin state) are updated early in the instruction after Read-Mod-
ify-Write instruction cycle.
Description
Logical AND
Logical OR
Logical EX-OR
Jump if bit = 1 and clear bit
Complement bit
Increment
Decrement
Decrement and jump if not zero
Move carry bit to bit y of Port x
Clear bit y of Port x
Set bit y of Port x
Example
ANL P1, A
ORL P2, A
XRL P3, A
JBC P1.1, LABEL
CPL P3.0
INC P2
DEC P2
DJNZ P3, LABEL
MOV P1.5, C
CLR P2.4
SET P3.3
4128G–8051–02/08