AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 435

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

22.5.6
22.5.7
22.5.8
9166C–AVR-08/11
Error bits
Bus Error Responses
Disabling the SAU
If error bits are set when attempting to unlock a channel, SR.URES will be set. The following SR
bits are considered error bits:
By writing a one to the Bus Error Response Enable bit (CR.BERREN), serious access errors will
be configured to return a bus error to the CPU. This will cause the CPU to execute its Bus Error
Data Fetch exception routine.
The conditions that can generate a bus error response are:
To disable the SAU, the user must first ensure that no SAU bus operations are pending. This
can be done by checking that the SR.IDLE bit is set.
The SAU may then be disabled by writing a one to the Disable (DIS) bit in CR.
• Unlock Register Error Status (URES) is set if an attempt was made to unlock a channel by
• Unlock Register Key Error (URKEY) is set if the Unlock Register was attempted written with
• Unlock Register Read (URREAD) is set if the Unlock Register was attempted read.
• Channel Access Unsuccessful (CAU) is set if the channel access was unsuccessful.
• Channel Access Successful (CAS) is set if the channel access was successful.
• Channel Unlock Expired (EXP) is set if the channel lock expired, with no channel being
• EXP
• CAU
• URREAD
• URKEY
• URES
• MBERROR
• RTRADR
• Reading the Unlock Register
• Trying to access a locked channel
• The SAU HSB master receiving a bus error response from its addressed slave
writing to the Unlock Register while one or more error bits in SR were set (see
22.5.6). The unlock operation was aborted.
an invalid key.
accessed after the channel was unlocked.
AT32UC3C
Section
435