AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 768
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #2
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
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29.6.3.2
29.6.3.3
9166C–AVR-08/11
Transmission
Reception
Figure 29-9. Identifier Mask (IDM)
Figure 29-10. Data Fields (64 bits)
Once a message has been written into RAM at the address corresponding to the selected MOb,
user controls transmission through the MOBCTRL register:
Once MOb is enabled (by writing to MOBER), transmission starts as soon as bus idle is detected
on the CAN bus. User can check if channel is sending a frame by reading CANSR.TS bit.
At the end of the successful transmission bit MOBESR.MENn is cleared and MOBSR.TXOK is
set. To acknowledge interrupt and to free the MOb user must clear this status bit by writing a one
to the associated bit in MOb Status Clear Register (MOBSCR).
CAN errors detected during transmission are reported in CANISR. Message will not be transmit-
ted but the MOb remains enabled. The message will be automatically re-transmitted until
successfully transmitted.
Several MObs can be enabled/disabled in one operation by writing to the MOBER/MOBDR
registers:
If several MObs are enabled, the MOb with the lowest number is transmitted first. This rule is
also used in case of a re-transmission (due to transmission error or contention).
Once the expected message has been written into RAM at the address corresponding to the
selected MOb, user controls reception through the MOBCTRL register:
• DLC[3:0] field: Data length code i.e. the number of byte to send, from 0 to 8
• DIR bit: MOb direction, 1 stands for transmission
• MOBER: Each bit correspond to an enable bit for a single MOb. Write 1 to set a bit and 0 to
• MOBDR: Each bit correspond to an enable bit for a single MOb. Write 1 to clear a bit and 0 to
• DLC[3:0] field: Data length code i.e. the number of byte to receive, from 0 to 8
keep it unchanged.
keep it unchanged.
31
31
31
-
-
DB3
DB7
RTRM IDEM
RTRM IDEM
30
30
24
29
29
23
28
28
DB2
DB6
16
-
15
IDM (29 bits)
11
DB1
DB5
10
8
IDM (11 bits)
7
DB0
DB4
0
0
0
Standard format
Extended format
@
@+4
AT32UC3C
768
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