AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 579

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

Figure 25-18. FSK Modulator Output
25.6.3.6
25.6.3.7
9166C–AVR-08/11
Uptstream Frequencies
unipolar output
FSK Modulator
default polarity
[F0, F0+offset]
NRZ stream
Manchester
Synchronous Receiver
Receiver Operations
encoded
Output
data
Txd
1
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 25-19
Figure 25-19. Synchronous Mode Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register
(RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while
the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into
RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register
(CR) with the RSTSTA (Reset Status) bit at 1.
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Sampling
Clock
RXD
illustrates a character reception in synchronous mode.
Start
0
D0
D1
D2
0
D3
D4
D5
D6
D7
1
AT32UC3C
Parity Bit
Stop Bit
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