AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 658

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

26.7.2
Figure 26-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
9166C–AVR-08/11
SPCK cycle (for reference)
Data Transfer
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
(to slave)
SPCK
SPCK
MOSI
MISO
NSS
Four combinations of polarity and phase are available for data transfers. The clock polarity is
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resulting in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
Table 26-2 on page 658
Table 26-2.
Figure 26-3 on page 658
MSB
1
MSB
*** Not Defined, but normaly MSB of previous character received
SPI modes
2
6
6
SPI Mode
0
1
2
3
3
shows the four modes and corresponding parameter settings.
and
5
5
Figure 26-4 on page 659
4
4
4
5
3
3
6
2
2
show examples of data transfers.
7
CPOL
1
1
0
0
1
1
8
LSB
LSB
***
AT32UC3C
NCPHA
1
0
1
0
658