AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 889

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

32.6.2.16
32.6.2.17
32.6.2.18
9166C–AVR-08/11
Data flow error
CRC error
Interrupts
• Global interrupts
This error exists only for isochronous IN/OUT endpoints. It sets the Errorflow Interrupt
(ERRORFI) bit in UESTAn, which triggers an EPnINT interrupt if the Errorflow Interrupt Enable
(ERRORFE) bit is one. The user can check the EPn_CTR_STA_BK0/1.UNDERF and OVERF
bits in the endpoint descriptor to see which current bank has been affected.
This error exists only for isochronous OUT endpoints. It sets the CRC Error Interrupt (CRCERRI)
bit in UESTAn, which triggers an EPnINT interrupt if the CRC Error Interrupt Enable
(CRCERRE) bit is one.
A CRC error can occur during an isochronous OUT stage if the USBC detects a corrupted
received packet. The OUT packet is stored in the bank as if no CRC error had occurred
(RXOUTI is set).
The user can also check the endpoint descriptor to see which current bank is impacted by the
CRC error by reading EPn_CTR_STA_BK0/1.CRCERR.
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors not related to CPU exceptions.
The processing device global interrupts are:
The exception device global interrupts are:
• A packet has been successfully received and the updated BYTE_COUNT equals the
• A short packet (smaller than EPSIZE) has been received.
• An underflow can occur during IN stage if the host attempts to read from an empty bank. A
• An overflow can occur during the OUT stage if the host tries to send a packet while the bank
• The Suspend (SUSP) interrupt
• The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number
• The End of Reset (EORST) interrupt
• The Wakeup (WAKEUP) interrupt
• The End of Resume (EORSM) interrupt
• The Upstream Resume (UPRSM) interrupt
• The Endpoint n (EPnINT) interrupt
MULTI_PACKET_SIZE.
zero-length packet is then automatically sent by the USBC. The endpoint descriptor
EPn_CTR_STA_BK0/1.UNDERF points out the bank from which the IN data should have
originated. If a new successful transaction occurs, the UNDERF bit is overwritten to 0 only if
the UESTAn.ERRORFI is cleared.
is full. Typically this occurs when a CPU is not fast enough. The packet data is not written to
the bank and is lost. The endpoint descriptor EPn_CTR_STA_BK0/1.OVERF points out
which bank the OUT data was destined to. If the UESTAn.ERRORFI bit is cleared and a new
transaction is successful, the OVERF bit will be overwritten to zero.
CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero)
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