AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 627
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
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Table 25-17.
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Table 25-18.
9166C–AVR-08/11
INACK: Inhibit Non Acknowledge
OVER: Oversampling Mode
CLKO: Clock Output Select
MODE9: 9-bit Character Length
MSBF/CPOL: Bit Order or SPI Clock Polarity
CHMODE: Channel Mode
NBSTOP: Number of Stop Bits
0
0
1
1
0
0
1
1
CHMODE
NBSTOP
0: The NACK is generated.
1: The NACK is not generated.
Note: in SPI master mode, if INACK = 0 the character transmission starts as soon as character is written into THR register
0: 16x Oversampling.
1: 8x Oversampling.
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin if USCLKS does not select the external clock CLK.
0: CHRL defines character length.
1: 9-bit character length.
If USART does not operate in SPI Mode (MODE … 0xE and 0xF):
MSBF = 0: Least Significant Bit is sent/received first.
MSBF = 1: Most Significant Bit is sent/received first.
If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
(assuming TXRDY was set). When INACK = 1, an additional condition must be met. The character transmission starts when a
character is written and only if RXRDY bit is cleared (RHR has been read).
clock/data relationship between master and slave devices.
0
1
0
1
0
1
0
1
Mode Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input.
Remote Loopback. RXD pin is internally connected to the TXD pin.
Asynchronous (SYNC = 0)
1 stop bit
1.5 stop bits
2 stop bits
Reserved
Synchronous (SYNC = 1)
1 stop bit
Reserved
2 stop bits
Reserved
AT32UC3C
627
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