SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 389

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

23.8.5
23.8.6
Table 23-2.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Coded Value
setup [5:0]
pulse [6:0]
cycle [8:0]
Write Protected Registers
Coding Timing Parameters
Coding and Range of Timing Parameters
Number of Bits
To prevent any single software error that may corrupt SMC behavior, the registers listed below
can be write-protected by setting the WPEN bit in the SMC Write Protect Mode Register
(SMC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write
Protect Status Register (SMC_WPSR) is set and the field WPVSRC indicates in which register
the write access has been attempted.
The WPVS flag is automatically reset after reading the SMC Write Protect Status Register
(SMC_WPSR).
List of the write-protected registers:
All timing parameters are defined for one chip select and are grouped together in one
SMC_REGISTER according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
Table 23-2
•
•
•
•
6
7
9
Section 23.15.1 ”SMC Setup Register”
Section 23.15.2 ”SMC Pulse Register”
Section 23.15.3 ”SMC Cycle Register”
Section 23.15.4 ”SMC MODE Register”
shows how the timing parameters are coded and their permitted range.
256 x cycle[8:7] + cycle[6:0]
128 x setup[5] + setup[4:0]
256 x pulse[6] + pulse[5:0]
Effective Value
Coded Value
0 ≤ ≤ 127
0 ≤ ≤ 31
0 ≤ ≤ 63
Permitted Range
SAM3S8/SD8
SAM3S8/SD8
Effective Value
0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
0 ≤ ≤ 128+31
0 ≤ ≤ 256+63
389
389